mpp_soc.cpp 36 KB

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  1. /*
  2. * Copyright 2020 Rockchip Electronics Co. LTD
  3. *
  4. * Licensed under the Apache License, Version 2.0 (the "License");
  5. * you may not use this file except in compliance with the License.
  6. * You may obtain a copy of the License at
  7. *
  8. * http://www.apache.org/licenses/LICENSE-2.0
  9. *
  10. * Unless required by applicable law or agreed to in writing, software
  11. * distributed under the License is distributed on an "AS IS" BASIS,
  12. * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  13. * See the License for the specific language governing permissions and
  14. * limitations under the License.
  15. */
  16. #define MODULE_TAG "mpp_soc"
  17. #include <sys/ioctl.h>
  18. #include <errno.h>
  19. #include <fcntl.h>
  20. #include <string.h>
  21. #include "mpp_debug.h"
  22. #include "mpp_common.h"
  23. #include "mpp_soc.h"
  24. #include "mpp_platform.h"
  25. #define MAX_SOC_NAME_LENGTH 128
  26. #define CODING_TO_IDX(type) \
  27. ((RK_U32)(type) >= (RK_U32)MPP_VIDEO_CodingKhronosExtensions) ? \
  28. ((RK_U32)(-1)) : \
  29. ((RK_U32)(type) >= (RK_U32)MPP_VIDEO_CodingVC1) ? \
  30. ((RK_U32)(type) - (RK_U32)MPP_VIDEO_CodingVC1 + 16) : \
  31. ((RK_U32)(type) - (RK_U32)MPP_VIDEO_CodingUnused)
  32. #define HAVE_MPEG2 ((RK_U32)(1 << (CODING_TO_IDX(MPP_VIDEO_CodingMPEG2))))
  33. #define HAVE_H263 ((RK_U32)(1 << (CODING_TO_IDX(MPP_VIDEO_CodingH263))))
  34. #define HAVE_MPEG4 ((RK_U32)(1 << (CODING_TO_IDX(MPP_VIDEO_CodingMPEG4))))
  35. #define HAVE_AVC ((RK_U32)(1 << (CODING_TO_IDX(MPP_VIDEO_CodingAVC))))
  36. #define HAVE_MJPEG ((RK_U32)(1 << (CODING_TO_IDX(MPP_VIDEO_CodingMJPEG))))
  37. #define HAVE_VP8 ((RK_U32)(1 << (CODING_TO_IDX(MPP_VIDEO_CodingVP8))))
  38. #define HAVE_VP9 ((RK_U32)(1 << (CODING_TO_IDX(MPP_VIDEO_CodingVP9))))
  39. #define HAVE_HEVC ((RK_U32)(1 << (CODING_TO_IDX(MPP_VIDEO_CodingHEVC))))
  40. #define HAVE_AVSP ((RK_U32)(1 << (CODING_TO_IDX(MPP_VIDEO_CodingAVSPLUS))))
  41. #define HAVE_AVS ((RK_U32)(1 << (CODING_TO_IDX(MPP_VIDEO_CodingAVS))))
  42. #define HAVE_AVS2 ((RK_U32)(1 << (CODING_TO_IDX(MPP_VIDEO_CodingAVS2))))
  43. #define HAVE_AV1 ((RK_U32)(1 << (CODING_TO_IDX(MPP_VIDEO_CodingAV1))))
  44. #define CAP_CODING_VDPU (HAVE_MPEG2|HAVE_H263|HAVE_MPEG4|HAVE_AVC|HAVE_MJPEG|HAVE_VP8|HAVE_AVS)
  45. #define CAP_CODING_JPEGD_PP (HAVE_MJPEG)
  46. #define CAP_CODING_AVSD (HAVE_AVS)
  47. #define CAP_CODING_AVSPD (HAVE_AVSP)
  48. #define CAP_CODING_AV1D (HAVE_AV1)
  49. #define CAP_CODING_HEVC (HAVE_HEVC)
  50. #define CAP_CODING_VDPU341 (HAVE_AVC|HAVE_HEVC|HAVE_VP9)
  51. #define CAP_CODING_VDPU341_LITE (HAVE_AVC|HAVE_HEVC)
  52. #define CAP_CODING_VDPU381 (HAVE_AVC|HAVE_HEVC|HAVE_VP9|HAVE_AVS2)
  53. #define CAP_CODING_VDPU382 (HAVE_AVC|HAVE_HEVC|HAVE_AVS2)
  54. #define CAP_CODING_VDPU383 (HAVE_AVC|HAVE_HEVC|HAVE_VP9|HAVE_AVS2|HAVE_AV1)
  55. #define CAP_CODING_VDPU384A (HAVE_AVC|HAVE_HEVC)
  56. #define CAP_CODING_VEPU1 (HAVE_AVC|HAVE_MJPEG|HAVE_VP8)
  57. #define CAP_CODING_VEPU_LITE (HAVE_AVC|HAVE_MJPEG)
  58. #define CAP_CODING_VEPU22 (HAVE_HEVC)
  59. #define CAP_CODING_VEPU54X (HAVE_AVC|HAVE_HEVC)
  60. #define CAP_CODING_VEPU540C (HAVE_AVC|HAVE_HEVC|HAVE_MJPEG)
  61. #define CAP_CODING_VEPU511 (HAVE_AVC|HAVE_HEVC|HAVE_MJPEG)
  62. static const MppDecHwCap vdpu1 = {
  63. .cap_coding = CAP_CODING_VDPU,
  64. .type = VPU_CLIENT_VDPU1,
  65. .cap_fbc = 0,
  66. .cap_4k = 0,
  67. .cap_8k = 0,
  68. .cap_colmv_compress = 0,
  69. .cap_hw_h265_rps = 0,
  70. .cap_hw_vp9_prob = 0,
  71. .cap_jpg_pp_out = 0,
  72. .cap_10bit = 0,
  73. .cap_down_scale = 0,
  74. .cap_lmt_linebuf = 1,
  75. .cap_core_num = 1,
  76. .cap_hw_jpg_fix = 0,
  77. .reserved = 0,
  78. };
  79. static const MppDecHwCap vdpu1_2160p = {
  80. .cap_coding = CAP_CODING_VDPU,
  81. .type = VPU_CLIENT_VDPU1,
  82. .cap_fbc = 0,
  83. .cap_4k = 1,
  84. .cap_8k = 0,
  85. .cap_colmv_compress = 0,
  86. .cap_hw_h265_rps = 0,
  87. .cap_hw_vp9_prob = 0,
  88. .cap_jpg_pp_out = 0,
  89. .cap_10bit = 0,
  90. .cap_down_scale = 0,
  91. .cap_lmt_linebuf = 1,
  92. .cap_core_num = 1,
  93. .cap_hw_jpg_fix = 0,
  94. .reserved = 0,
  95. };
  96. static const MppDecHwCap vdpu1_jpeg_pp = {
  97. .cap_coding = CAP_CODING_JPEGD_PP,
  98. .type = VPU_CLIENT_VDPU1_PP,
  99. .cap_fbc = 0,
  100. .cap_4k = 1,
  101. .cap_8k = 1,
  102. .cap_colmv_compress = 0,
  103. .cap_hw_h265_rps = 0,
  104. .cap_hw_vp9_prob = 0,
  105. .cap_jpg_pp_out = 1,
  106. .cap_10bit = 0,
  107. .cap_down_scale = 0,
  108. .cap_lmt_linebuf = 1,
  109. .cap_core_num = 1,
  110. .cap_hw_jpg_fix = 0,
  111. .reserved = 0,
  112. };
  113. static const MppDecHwCap vdpu2 = {
  114. .cap_coding = CAP_CODING_VDPU,
  115. .type = VPU_CLIENT_VDPU2,
  116. .cap_fbc = 0,
  117. .cap_4k = 0,
  118. .cap_8k = 0,
  119. .cap_colmv_compress = 0,
  120. .cap_hw_h265_rps = 0,
  121. .cap_hw_vp9_prob = 0,
  122. .cap_jpg_pp_out = 0,
  123. .cap_10bit = 0,
  124. .cap_down_scale = 0,
  125. .cap_lmt_linebuf = 1,
  126. .cap_core_num = 1,
  127. .cap_hw_jpg_fix = 0,
  128. .reserved = 0,
  129. };
  130. static const MppDecHwCap vdpu2_jpeg = {
  131. .cap_coding = HAVE_MJPEG,
  132. .type = VPU_CLIENT_VDPU2,
  133. .cap_fbc = 0,
  134. .cap_4k = 0,
  135. .cap_8k = 0,
  136. .cap_colmv_compress = 0,
  137. .cap_hw_h265_rps = 0,
  138. .cap_hw_vp9_prob = 0,
  139. .cap_jpg_pp_out = 0,
  140. .cap_10bit = 0,
  141. .cap_down_scale = 0,
  142. .cap_lmt_linebuf = 1,
  143. .cap_core_num = 1,
  144. .cap_hw_jpg_fix = 0,
  145. .reserved = 0,
  146. };
  147. static const MppDecHwCap vdpu2_jpeg_pp = {
  148. .cap_coding = CAP_CODING_JPEGD_PP,
  149. .type = VPU_CLIENT_VDPU2_PP,
  150. .cap_fbc = 0,
  151. .cap_4k = 0,
  152. .cap_8k = 0,
  153. .cap_colmv_compress = 0,
  154. .cap_hw_h265_rps = 0,
  155. .cap_hw_vp9_prob = 0,
  156. .cap_jpg_pp_out = 1,
  157. .cap_10bit = 0,
  158. .cap_down_scale = 0,
  159. .cap_lmt_linebuf = 1,
  160. .cap_core_num = 1,
  161. .cap_hw_jpg_fix = 0,
  162. .reserved = 0,
  163. };
  164. static const MppDecHwCap vdpu2_jpeg_fix = {
  165. .cap_coding = HAVE_MJPEG,
  166. .type = VPU_CLIENT_VDPU2,
  167. .cap_fbc = 0,
  168. .cap_4k = 0,
  169. .cap_8k = 0,
  170. .cap_colmv_compress = 0,
  171. .cap_hw_h265_rps = 0,
  172. .cap_hw_vp9_prob = 0,
  173. .cap_jpg_pp_out = 0,
  174. .cap_10bit = 0,
  175. .cap_down_scale = 0,
  176. .cap_lmt_linebuf = 1,
  177. .cap_core_num = 1,
  178. .cap_hw_jpg_fix = 1,
  179. .reserved = 0,
  180. };
  181. static const MppDecHwCap vdpu2_jpeg_pp_fix = {
  182. .cap_coding = CAP_CODING_JPEGD_PP,
  183. .type = VPU_CLIENT_VDPU2_PP,
  184. .cap_fbc = 0,
  185. .cap_4k = 0,
  186. .cap_8k = 0,
  187. .cap_colmv_compress = 0,
  188. .cap_hw_h265_rps = 0,
  189. .cap_hw_vp9_prob = 0,
  190. .cap_jpg_pp_out = 1,
  191. .cap_10bit = 0,
  192. .cap_down_scale = 0,
  193. .cap_lmt_linebuf = 1,
  194. .cap_core_num = 1,
  195. .cap_hw_jpg_fix = 1,
  196. .reserved = 0,
  197. };
  198. static const MppDecHwCap rk_hevc = {
  199. .cap_coding = CAP_CODING_HEVC,
  200. .type = VPU_CLIENT_HEVC_DEC,
  201. .cap_fbc = 0,
  202. .cap_4k = 1,
  203. .cap_8k = 0,
  204. .cap_colmv_compress = 0,
  205. .cap_hw_h265_rps = 0,
  206. .cap_hw_vp9_prob = 0,
  207. .cap_jpg_pp_out = 0,
  208. .cap_10bit = 1,
  209. .cap_down_scale = 0,
  210. .cap_lmt_linebuf = 1,
  211. .cap_core_num = 1,
  212. .cap_hw_jpg_fix = 0,
  213. .reserved = 0,
  214. };
  215. static const MppDecHwCap rk_hevc_1080p = {
  216. .cap_coding = CAP_CODING_HEVC,
  217. .type = VPU_CLIENT_HEVC_DEC,
  218. .cap_fbc = 0,
  219. .cap_4k = 0,
  220. .cap_8k = 0,
  221. .cap_colmv_compress = 0,
  222. .cap_hw_h265_rps = 0,
  223. .cap_hw_vp9_prob = 0,
  224. .cap_jpg_pp_out = 0,
  225. .cap_10bit = 0,
  226. .cap_down_scale = 0,
  227. .cap_lmt_linebuf = 1,
  228. .cap_core_num = 1,
  229. .cap_hw_jpg_fix = 0,
  230. .reserved = 0,
  231. };
  232. static const MppDecHwCap vdpu341 = {
  233. .cap_coding = CAP_CODING_VDPU341,
  234. .type = VPU_CLIENT_RKVDEC,
  235. .cap_fbc = 0,
  236. .cap_4k = 1,
  237. .cap_8k = 0,
  238. .cap_colmv_compress = 1,
  239. .cap_hw_h265_rps = 0,
  240. .cap_hw_vp9_prob = 0,
  241. .cap_jpg_pp_out = 0,
  242. .cap_10bit = 1,
  243. .cap_down_scale = 0,
  244. .cap_lmt_linebuf = 1,
  245. .cap_core_num = 1,
  246. .cap_hw_jpg_fix = 0,
  247. .reserved = 0,
  248. };
  249. static const MppDecHwCap vdpu341_lite = {
  250. .cap_coding = CAP_CODING_VDPU341_LITE,
  251. .type = VPU_CLIENT_RKVDEC,
  252. .cap_fbc = 0,
  253. .cap_4k = 1,
  254. .cap_8k = 0,
  255. .cap_colmv_compress = 1,
  256. .cap_hw_h265_rps = 0,
  257. .cap_hw_vp9_prob = 0,
  258. .cap_jpg_pp_out = 0,
  259. .cap_10bit = 1,
  260. .cap_down_scale = 0,
  261. .cap_lmt_linebuf = 1,
  262. .cap_core_num = 1,
  263. .cap_hw_jpg_fix = 0,
  264. .reserved = 0,
  265. };
  266. static const MppDecHwCap vdpu341_lite_1080p = {
  267. .cap_coding = CAP_CODING_VDPU341_LITE,
  268. .type = VPU_CLIENT_RKVDEC,
  269. .cap_fbc = 0,
  270. .cap_4k = 0,
  271. .cap_8k = 0,
  272. .cap_colmv_compress = 1,
  273. .cap_hw_h265_rps = 0,
  274. .cap_hw_vp9_prob = 0,
  275. .cap_jpg_pp_out = 0,
  276. .cap_10bit = 0,
  277. .cap_down_scale = 0,
  278. .cap_lmt_linebuf = 1,
  279. .cap_core_num = 1,
  280. .cap_hw_jpg_fix = 0,
  281. .reserved = 0,
  282. };
  283. static const MppDecHwCap vdpu341_h264 = {
  284. .cap_coding = HAVE_AVC,
  285. .type = VPU_CLIENT_RKVDEC,
  286. .cap_fbc = 0,
  287. .cap_4k = 1,
  288. .cap_8k = 0,
  289. .cap_colmv_compress = 1,
  290. .cap_hw_h265_rps = 0,
  291. .cap_hw_vp9_prob = 0,
  292. .cap_jpg_pp_out = 0,
  293. .cap_10bit = 0,
  294. .cap_down_scale = 0,
  295. .cap_lmt_linebuf = 1,
  296. .cap_core_num = 1,
  297. .cap_hw_jpg_fix = 0,
  298. .reserved = 0,
  299. };
  300. /* vdpu34x support AFBC_V2 output */
  301. static const MppDecHwCap vdpu34x = {
  302. .cap_coding = CAP_CODING_VDPU341,
  303. .type = VPU_CLIENT_RKVDEC,
  304. .cap_fbc = 2,
  305. .cap_4k = 1,
  306. .cap_8k = 1,
  307. .cap_colmv_compress = 1,
  308. .cap_hw_h265_rps = 1,
  309. .cap_hw_vp9_prob = 1,
  310. .cap_jpg_pp_out = 0,
  311. .cap_10bit = 1,
  312. .cap_down_scale = 0,
  313. .cap_lmt_linebuf = 0,
  314. .cap_core_num = 1,
  315. .cap_hw_jpg_fix = 0,
  316. .reserved = 0,
  317. };
  318. static const MppDecHwCap vdpu38x = {
  319. .cap_coding = CAP_CODING_VDPU381,
  320. .type = VPU_CLIENT_RKVDEC,
  321. .cap_fbc = 2,
  322. .cap_4k = 1,
  323. .cap_8k = 1,
  324. .cap_colmv_compress = 1,
  325. .cap_hw_h265_rps = 1,
  326. .cap_hw_vp9_prob = 1,
  327. .cap_jpg_pp_out = 0,
  328. .cap_10bit = 1,
  329. .cap_down_scale = 1,
  330. .cap_lmt_linebuf = 0,
  331. .cap_core_num = 2,
  332. .cap_hw_jpg_fix = 0,
  333. .reserved = 0,
  334. };
  335. static const MppDecHwCap vdpu382a = {
  336. .cap_coding = CAP_CODING_VDPU381,
  337. .type = VPU_CLIENT_RKVDEC,
  338. .cap_fbc = 2,
  339. .cap_4k = 1,
  340. .cap_8k = 1,
  341. .cap_colmv_compress = 1,
  342. .cap_hw_h265_rps = 1,
  343. .cap_hw_vp9_prob = 1,
  344. .cap_jpg_pp_out = 0,
  345. .cap_10bit = 1,
  346. .cap_down_scale = 1,
  347. .cap_lmt_linebuf = 0,
  348. .cap_core_num = 1,
  349. .cap_hw_jpg_fix = 0,
  350. .reserved = 0,
  351. };
  352. static const MppDecHwCap vdpu382 = {
  353. .cap_coding = CAP_CODING_VDPU382,
  354. .type = VPU_CLIENT_RKVDEC,
  355. .cap_fbc = 2,
  356. .cap_4k = 1,
  357. .cap_8k = 1,
  358. .cap_colmv_compress = 1,
  359. .cap_hw_h265_rps = 1,
  360. .cap_hw_vp9_prob = 1,
  361. .cap_jpg_pp_out = 0,
  362. .cap_10bit = 1,
  363. .cap_down_scale = 1,
  364. .cap_lmt_linebuf = 0,
  365. .cap_core_num = 1,
  366. .cap_hw_jpg_fix = 0,
  367. .reserved = 0,
  368. };
  369. static const MppDecHwCap vdpu382_lite = {
  370. .cap_coding = CAP_CODING_VDPU341,
  371. .type = VPU_CLIENT_RKVDEC,
  372. .cap_fbc = 0,
  373. .cap_4k = 1,
  374. .cap_8k = 1,
  375. .cap_colmv_compress = 0,
  376. .cap_hw_h265_rps = 1,
  377. .cap_hw_vp9_prob = 1,
  378. .cap_jpg_pp_out = 0,
  379. .cap_10bit = 0,
  380. .cap_down_scale = 1,
  381. .cap_lmt_linebuf = 0,
  382. .cap_core_num = 1,
  383. .cap_hw_jpg_fix = 0,
  384. .reserved = 0,
  385. };
  386. static const MppDecHwCap vdpu383 = {
  387. .cap_coding = CAP_CODING_VDPU383,
  388. .type = VPU_CLIENT_RKVDEC,
  389. .cap_fbc = 2,
  390. .cap_4k = 1,
  391. .cap_8k = 1,
  392. .cap_colmv_compress = 1,
  393. .cap_hw_h265_rps = 1,
  394. .cap_hw_vp9_prob = 1,
  395. .cap_jpg_pp_out = 0,
  396. .cap_10bit = 1,
  397. .cap_down_scale = 1,
  398. .cap_lmt_linebuf = 0,
  399. .cap_core_num = 1,
  400. .cap_hw_jpg_fix = 0,
  401. .reserved = 0,
  402. };
  403. static const MppDecHwCap vdpu384a = {
  404. .cap_coding = CAP_CODING_VDPU384A,
  405. .type = VPU_CLIENT_RKVDEC,
  406. .cap_fbc = 0,
  407. .cap_4k = 1,
  408. .cap_8k = 1,
  409. .cap_colmv_compress = 1,
  410. .cap_hw_h265_rps = 1,
  411. .cap_hw_vp9_prob = 0,
  412. .cap_jpg_pp_out = 0,
  413. .cap_10bit = 1,
  414. .cap_down_scale = 1,
  415. .cap_lmt_linebuf = 0,
  416. .cap_core_num = 1,
  417. .cap_hw_jpg_fix = 0,
  418. .reserved = 0,
  419. };
  420. static const MppDecHwCap avspd = {
  421. .cap_coding = CAP_CODING_AVSPD,
  422. .type = VPU_CLIENT_AVSPLUS_DEC,
  423. .cap_fbc = 0,
  424. .cap_4k = 0,
  425. .cap_8k = 0,
  426. .cap_colmv_compress = 0,
  427. .cap_hw_h265_rps = 0,
  428. .cap_hw_vp9_prob = 0,
  429. .cap_jpg_pp_out = 0,
  430. .cap_10bit = 0,
  431. .cap_down_scale = 0,
  432. .cap_lmt_linebuf = 1,
  433. .cap_core_num = 1,
  434. .cap_hw_jpg_fix = 0,
  435. .reserved = 0,
  436. };
  437. static const MppDecHwCap rkjpegd = {
  438. .cap_coding = HAVE_MJPEG,
  439. .type = VPU_CLIENT_JPEG_DEC,
  440. .cap_fbc = 0,
  441. .cap_4k = 1,
  442. .cap_8k = 0,
  443. .cap_colmv_compress = 0,
  444. .cap_hw_h265_rps = 0,
  445. .cap_hw_vp9_prob = 0,
  446. .cap_jpg_pp_out = 0,
  447. .cap_10bit = 0,
  448. .cap_down_scale = 0,
  449. .cap_lmt_linebuf = 0,
  450. .cap_core_num = 1,
  451. .cap_hw_jpg_fix = 1,
  452. .reserved = 0,
  453. };
  454. static const MppDecHwCap av1d = {
  455. .cap_coding = CAP_CODING_AV1D,
  456. .type = VPU_CLIENT_AV1DEC,
  457. .cap_fbc = 1,
  458. .cap_4k = 1,
  459. .cap_8k = 0,
  460. .cap_colmv_compress = 0,
  461. .cap_hw_h265_rps = 0,
  462. .cap_hw_vp9_prob = 0,
  463. .cap_jpg_pp_out = 0,
  464. .cap_10bit = 0,
  465. .cap_down_scale = 0,
  466. .cap_lmt_linebuf = 1,
  467. .cap_core_num = 1,
  468. .cap_hw_jpg_fix = 0,
  469. .reserved = 0,
  470. };
  471. static const MppEncHwCap vepu1 = {
  472. .cap_coding = CAP_CODING_VEPU1,
  473. .type = VPU_CLIENT_VEPU1,
  474. .cap_fbc = 0,
  475. .cap_4k = 0,
  476. .cap_8k = 0,
  477. .cap_hw_osd = 0,
  478. .cap_hw_roi = 0,
  479. .reserved = 0,
  480. };
  481. static const MppEncHwCap vepu2 = {
  482. .cap_coding = CAP_CODING_VEPU1,
  483. .type = VPU_CLIENT_VEPU2,
  484. .cap_fbc = 0,
  485. .cap_4k = 0,
  486. .cap_8k = 0,
  487. .cap_hw_osd = 0,
  488. .cap_hw_roi = 0,
  489. .reserved = 0,
  490. };
  491. static const MppEncHwCap vepu2_no_vp8 = {
  492. .cap_coding = HAVE_AVC | HAVE_MJPEG,
  493. .type = VPU_CLIENT_VEPU2,
  494. .cap_fbc = 0,
  495. .cap_4k = 0,
  496. .cap_8k = 0,
  497. .cap_hw_osd = 0,
  498. .cap_hw_roi = 0,
  499. .reserved = 0,
  500. };
  501. static const MppEncHwCap vepu2_no_jpeg = {
  502. .cap_coding = HAVE_AVC | HAVE_VP8,
  503. .type = VPU_CLIENT_VEPU2,
  504. .cap_fbc = 0,
  505. .cap_4k = 0,
  506. .cap_8k = 0,
  507. .cap_hw_osd = 0,
  508. .cap_hw_roi = 0,
  509. .reserved = 0,
  510. };
  511. static const MppEncHwCap vepu2_jpeg = {
  512. .cap_coding = HAVE_MJPEG,
  513. .type = VPU_CLIENT_VEPU2,
  514. .cap_fbc = 0,
  515. .cap_4k = 0,
  516. .cap_8k = 0,
  517. .cap_hw_osd = 0,
  518. .cap_hw_roi = 0,
  519. .reserved = 0,
  520. };
  521. static const MppEncHwCap vepu2_jpeg_enhanced = {
  522. .cap_coding = HAVE_MJPEG,
  523. .type = VPU_CLIENT_VEPU2_JPEG,
  524. .cap_fbc = 0,
  525. .cap_4k = 1,
  526. .cap_8k = 0,
  527. .cap_hw_osd = 0,
  528. .cap_hw_roi = 0,
  529. .reserved = 0,
  530. };
  531. static const MppEncHwCap vepu22 = {
  532. .cap_coding = CAP_CODING_HEVC,
  533. .type = VPU_CLIENT_VEPU22,
  534. .cap_fbc = 0,
  535. .cap_4k = 0,
  536. .cap_8k = 0,
  537. .cap_hw_osd = 0,
  538. .cap_hw_roi = 0,
  539. .reserved = 0,
  540. };
  541. static const MppEncHwCap vepu540p = {
  542. .cap_coding = HAVE_AVC,
  543. .type = VPU_CLIENT_RKVENC,
  544. .cap_fbc = 0,
  545. .cap_4k = 0,
  546. .cap_8k = 0,
  547. .cap_hw_osd = 1,
  548. .cap_hw_roi = 1,
  549. .reserved = 0,
  550. };
  551. static const MppEncHwCap vepu541 = {
  552. .cap_coding = CAP_CODING_VEPU54X,
  553. .type = VPU_CLIENT_RKVENC,
  554. .cap_fbc = 1,
  555. .cap_4k = 1,
  556. .cap_8k = 0,
  557. .cap_hw_osd = 1,
  558. .cap_hw_roi = 1,
  559. .reserved = 0,
  560. };
  561. /* vepu540 support both AFBC_V1 and AFBC_V2 input */
  562. static const MppEncHwCap vepu540 = {
  563. .cap_coding = CAP_CODING_VEPU54X,
  564. .type = VPU_CLIENT_RKVENC,
  565. .cap_fbc = 0x1 | 0x2,
  566. .cap_4k = 0,
  567. .cap_8k = 0,
  568. .cap_hw_osd = 1,
  569. .cap_hw_roi = 1,
  570. .reserved = 0,
  571. };
  572. /* vepu58x */
  573. static const MppEncHwCap vepu58x = {
  574. .cap_coding = CAP_CODING_VEPU54X,
  575. .type = VPU_CLIENT_RKVENC,
  576. .cap_fbc = 0x1 | 0x2,
  577. .cap_4k = 1,
  578. .cap_8k = 1,
  579. .cap_hw_osd = 1,
  580. .cap_hw_roi = 1,
  581. .reserved = 0,
  582. };
  583. static const MppEncHwCap vepu540c = {
  584. .cap_coding = CAP_CODING_VEPU540C,
  585. .type = VPU_CLIENT_RKVENC,
  586. .cap_fbc = 0x1 | 0x2,
  587. .cap_4k = 0,
  588. .cap_8k = 0,
  589. .cap_hw_osd = 0,
  590. .cap_hw_roi = 1,
  591. .reserved = 0,
  592. };
  593. static const MppEncHwCap vepu540c_no_hevc = {
  594. .cap_coding = (HAVE_AVC | HAVE_MJPEG),
  595. .type = VPU_CLIENT_RKVENC,
  596. .cap_fbc = 0,
  597. .cap_4k = 1,
  598. .cap_8k = 1,
  599. .cap_hw_osd = 0,
  600. .cap_hw_roi = 1,
  601. .reserved = 0,
  602. };
  603. static const MppEncHwCap vepu510 = {
  604. .cap_coding = CAP_CODING_VEPU54X,
  605. .type = VPU_CLIENT_RKVENC,
  606. .cap_fbc = 0,
  607. .cap_4k = 1,
  608. .cap_8k = 1,
  609. .cap_hw_osd = 0,
  610. .cap_hw_roi = 1,
  611. .reserved = 0,
  612. };
  613. static const MppEncHwCap vepu511 = {
  614. .cap_coding = CAP_CODING_VEPU511,
  615. .type = VPU_CLIENT_RKVENC,
  616. .cap_fbc = 2,
  617. .cap_4k = 1,
  618. .cap_8k = 0,
  619. .cap_hw_osd = 1,
  620. .cap_hw_roi = 1,
  621. .reserved = 0,
  622. };
  623. static const MppEncHwCap rkjpege_vpu720 = {
  624. .cap_coding = HAVE_MJPEG,
  625. .type = VPU_CLIENT_JPEG_ENC,
  626. .cap_fbc = 0,
  627. .cap_4k = 1,
  628. .cap_8k = 1,
  629. .cap_hw_osd = 0,
  630. .cap_hw_roi = 0,
  631. .reserved = 0,
  632. };
  633. /*
  634. * NOTE:
  635. * vpu1 = vdpu1 + vepu1
  636. * vpu2 = vdpu2 + vepu2
  637. */
  638. static const MppSocInfo mpp_soc_infos[] = {
  639. { /*
  640. * rk3036 has
  641. * 1 - vdpu1
  642. * 2 - RK hevc decoder
  643. * rk3036 do NOT have encoder
  644. */
  645. "rk3036",
  646. ROCKCHIP_SOC_RK3036,
  647. HAVE_VDPU1 | HAVE_VDPU1_PP | HAVE_HEVC_DEC,
  648. { &rk_hevc_1080p, &vdpu1, &vdpu1_jpeg_pp, NULL, NULL, NULL, },
  649. { NULL, NULL, NULL, NULL, },
  650. },
  651. { /* rk3066 has vpu1 only */
  652. "rk3066",
  653. ROCKCHIP_SOC_RK3066,
  654. HAVE_VDPU1 | HAVE_VDPU1_PP | HAVE_VEPU1,
  655. { &vdpu1, &vdpu1_jpeg_pp, NULL, NULL, NULL, NULL, },
  656. { &vepu1, NULL, NULL, NULL, },
  657. },
  658. { /* rk3188 has vpu1 only */
  659. "rk3188",
  660. ROCKCHIP_SOC_RK3188,
  661. HAVE_VDPU1 | HAVE_VDPU1_PP | HAVE_VEPU1,
  662. { &vdpu1, &vdpu1_jpeg_pp, NULL, NULL, NULL, NULL, },
  663. { &vepu1, NULL, NULL, NULL, },
  664. },
  665. { /*
  666. * rk3288 has
  667. * 1 - vpu1 with 2160p AVC decoder
  668. * 2 - RK hevc 4K decoder
  669. */
  670. "rk3288",
  671. ROCKCHIP_SOC_RK3288,
  672. HAVE_VDPU1 | HAVE_VDPU1_PP | HAVE_VEPU1 | HAVE_HEVC_DEC,
  673. { &rk_hevc, &vdpu1_2160p, &vdpu1_jpeg_pp, NULL, NULL, NULL, },
  674. { &vepu1, NULL, NULL, NULL, },
  675. },
  676. { /*
  677. * rk3126 has
  678. * 1 - vpu1
  679. * 2 - RK hevc 1080p decoder
  680. */
  681. "rk3126",
  682. ROCKCHIP_SOC_RK312X,
  683. HAVE_VDPU1 | HAVE_VDPU1_PP | HAVE_VEPU1 | HAVE_HEVC_DEC,
  684. { &rk_hevc_1080p, &vdpu1, &vdpu1_jpeg_pp, NULL, NULL, NULL, },
  685. { &vepu1, NULL, NULL, NULL, },
  686. },
  687. { /*
  688. * rk3128 has
  689. * 1 - vpu1
  690. * 2 - RK hevc 1080p decoder
  691. */
  692. "rk3128",
  693. ROCKCHIP_SOC_RK312X,
  694. HAVE_VDPU1 | HAVE_VDPU1_PP | HAVE_VEPU1 | HAVE_HEVC_DEC,
  695. { &rk_hevc_1080p, &vdpu1, &vdpu1_jpeg_pp, NULL, NULL, NULL, },
  696. { &vepu1, NULL, NULL, NULL, },
  697. },
  698. { /*
  699. * rk3128h has
  700. * 1 - vpu2
  701. * 2 - RK H.264/H.265 1080p@60fps decoder
  702. * NOTE: rk3128H do NOT have jpeg encoder
  703. */
  704. "rk3128h",
  705. ROCKCHIP_SOC_RK3128H,
  706. HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_RKVDEC,
  707. { &vdpu341_lite_1080p, &vdpu2, &vdpu2_jpeg_pp, NULL, NULL, NULL, },
  708. { &vepu2_no_jpeg, NULL, NULL, NULL, },
  709. },
  710. { /*
  711. * rk3368 has
  712. * 1 - vpu1
  713. * 2 - RK hevc 4K decoder
  714. */
  715. "rk3368",
  716. ROCKCHIP_SOC_RK3368,
  717. HAVE_VDPU1 | HAVE_VDPU1_PP | HAVE_VEPU1 | HAVE_HEVC_DEC,
  718. { &rk_hevc, &vdpu1_2160p, &vdpu1_jpeg_pp, NULL, NULL, NULL, },
  719. { &vepu1, NULL, NULL, NULL, },
  720. },
  721. { /*
  722. * rk3399 has
  723. * 1 - vpu2
  724. * 2 - H.264/H.265/VP9 4K decoder
  725. */
  726. "rk3399",
  727. ROCKCHIP_SOC_RK3399,
  728. HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_RKVDEC,
  729. { &vdpu341, &vdpu2, &vdpu2_jpeg_pp, NULL, NULL, NULL, },
  730. { &vepu2, NULL, NULL, NULL, },
  731. },
  732. { /*
  733. * rk3328 has codec:
  734. * 1 - vpu2
  735. * 2 - RK H.264/H.265/VP9 4K decoder
  736. * 4 - H.265 encoder
  737. */
  738. "rk3328",
  739. ROCKCHIP_SOC_RK3328,
  740. HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_RKVDEC | HAVE_VEPU22,
  741. { &vdpu341, &vdpu2, &vdpu2_jpeg_pp, NULL, NULL, NULL, },
  742. { &vepu2, &vepu22, NULL, NULL, },
  743. },
  744. { /*
  745. * rk3228 have codec:
  746. * 1 - vpu2
  747. * 2 - RK H.264/H.265 4K decoder
  748. * NOTE: rk3228 do NOT have jpeg encoder
  749. */
  750. "rk3228",
  751. ROCKCHIP_SOC_RK3228,
  752. HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_RKVDEC,
  753. { &vdpu341_lite, &vdpu2, &vdpu2_jpeg_pp, NULL, NULL, NULL, },
  754. { &vepu2_no_jpeg, NULL, NULL, NULL, },
  755. },
  756. { /*
  757. * rk3228h has
  758. * 1 - vpu2
  759. * 2 - RK H.264/H.265 4K decoder
  760. * 3 - avs+ decoder
  761. * 4 - H.265 1080p encoder
  762. * rk3228h first for string matching
  763. */
  764. "rk3228h",
  765. ROCKCHIP_SOC_RK3228H,
  766. HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_RKVDEC | HAVE_AVSDEC | HAVE_VEPU22,
  767. { &vdpu341_lite, &vdpu2, &vdpu2_jpeg_pp, &avspd, NULL, NULL, },
  768. { &vepu2_no_jpeg, &vepu22, NULL, NULL, },
  769. },
  770. { /*
  771. * rk3229 has
  772. * 1 - vpu2
  773. * 2 - H.264/H.265/VP9 4K decoder
  774. */
  775. "rk3229",
  776. ROCKCHIP_SOC_RK3229,
  777. HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_RKVDEC,
  778. { &vdpu341, &vdpu2, &vdpu2_jpeg_pp, NULL, NULL, NULL, },
  779. { &vepu2, NULL, NULL, NULL, },
  780. },
  781. { /*
  782. * rv1108 has codec:
  783. * 1 - vpu2 for jpeg encoder and decoder
  784. * 2 - RK H.264 4K decoder
  785. * 3 - RK H.264 4K encoder
  786. */
  787. "rv1108",
  788. ROCKCHIP_SOC_RV1108,
  789. HAVE_VDPU2 | HAVE_VEPU2 | HAVE_RKVDEC | HAVE_RKVENC,
  790. { &vdpu2_jpeg, &vdpu341_h264, NULL, NULL, NULL, NULL, },
  791. { &vepu2_jpeg, &vepu540p, NULL, NULL, },
  792. },
  793. { /*
  794. * rv1109 has codec:
  795. * 1 - vpu2 for jpeg encoder and decoder
  796. * 2 - RK H.264/H.265 4K decoder
  797. * 3 - RK H.264/H.265 4K encoder
  798. */
  799. "rv1109",
  800. ROCKCHIP_SOC_RV1109,
  801. HAVE_VDPU2 | HAVE_VEPU2 | HAVE_RKVDEC | HAVE_RKVENC,
  802. { &vdpu2_jpeg_fix, &vdpu341_lite, NULL, NULL, NULL, NULL, },
  803. { &vepu2_jpeg, &vepu541, NULL, NULL, },
  804. },
  805. { /*
  806. * rv1126 has codec:
  807. * 1 - vpu2 for jpeg encoder and decoder
  808. * 2 - RK H.264/H.265 4K decoder
  809. * 3 - RK H.264/H.265 4K encoder
  810. */
  811. "rv1126",
  812. ROCKCHIP_SOC_RV1126,
  813. HAVE_VDPU2 | HAVE_VEPU2 | HAVE_RKVDEC | HAVE_RKVENC,
  814. { &vdpu2_jpeg_fix, &vdpu341_lite, NULL, NULL, NULL, NULL, },
  815. { &vepu2_jpeg, &vepu541, NULL, NULL, },
  816. },
  817. { /*
  818. * rk3326 has
  819. * 1 - vpu2
  820. * 2 - RK hevc 1080p decoder
  821. */
  822. "rk3326",
  823. ROCKCHIP_SOC_RK3326,
  824. HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_HEVC_DEC,
  825. { &rk_hevc_1080p, &vdpu2, &vdpu2_jpeg_pp_fix, NULL, NULL, NULL, },
  826. { &vepu2, NULL, NULL, NULL, },
  827. },
  828. { /*
  829. * px30 has
  830. * 1 - vpu2
  831. * 2 - RK hevc 1080p decoder
  832. */
  833. "px30",
  834. ROCKCHIP_SOC_RK3326,
  835. HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_HEVC_DEC,
  836. { &rk_hevc_1080p, &vdpu2, &vdpu2_jpeg_pp_fix, NULL, NULL, NULL, },
  837. { &vepu2, NULL, NULL, NULL, },
  838. },
  839. { /*
  840. * px30 has vpu2 only
  841. */
  842. "rk1808",
  843. ROCKCHIP_SOC_RK1808,
  844. HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2,
  845. { &vdpu2, &vdpu2_jpeg_pp, NULL, NULL, NULL, NULL, },
  846. { &vepu2, NULL, NULL, NULL, },
  847. },
  848. { /*
  849. * rk3566/rk3567/rk3568 has codec:
  850. * 1 - vpu2 for jpeg encoder and decoder
  851. * 2 - RK H.264/H.265/VP9 4K decoder
  852. * 3 - RK H.264/H.265 4K encoder
  853. * 3 - RK jpeg decoder
  854. */
  855. "rk3566",
  856. ROCKCHIP_SOC_RK3566,
  857. HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_RKVDEC | HAVE_RKVENC | HAVE_JPEG_DEC,
  858. { &vdpu34x, &rkjpegd, &vdpu2, &vdpu2_jpeg_pp_fix, NULL, NULL, },
  859. { &vepu540, &vepu2_no_vp8, NULL, NULL, },
  860. },
  861. { /*
  862. * rk3566/rk3567/rk3568 has codec:
  863. * 1 - vpu2 for jpeg encoder and decoder
  864. * 2 - RK H.264/H.265/VP9 4K decoder
  865. * 3 - RK H.264/H.265 4K encoder
  866. * 3 - RK jpeg decoder
  867. */
  868. "rk3567",
  869. ROCKCHIP_SOC_RK3567,
  870. HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_RKVDEC | HAVE_RKVENC | HAVE_JPEG_DEC,
  871. { &vdpu34x, &rkjpegd, &vdpu2, &vdpu2_jpeg_pp_fix, NULL, NULL, },
  872. { &vepu540, &vepu2_no_vp8, NULL, NULL, },
  873. },
  874. { /*
  875. * rk3566/rk3567/rk3568 has codec:
  876. * 1 - vpu2 for jpeg encoder and decoder
  877. * 2 - RK H.264/H.265/VP9 4K decoder
  878. * 3 - RK H.264/H.265 4K encoder
  879. * 3 - RK jpeg decoder
  880. */
  881. "rk3568",
  882. ROCKCHIP_SOC_RK3568,
  883. HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_RKVDEC | HAVE_RKVENC | HAVE_JPEG_DEC,
  884. { &vdpu34x, &rkjpegd, &vdpu2, &vdpu2_jpeg_pp_fix, NULL, NULL, },
  885. { &vepu540, &vepu2_no_vp8, NULL, NULL, },
  886. },
  887. { /*
  888. * rk3588 has codec:
  889. * 1 - vpu2 for jpeg/vp8 encoder and decoder
  890. * 2 - RK H.264/H.265/VP9 8K decoder
  891. * 3 - RK H.264/H.265 8K encoder
  892. * 4 - RK jpeg decoder
  893. */
  894. "rk3588",
  895. ROCKCHIP_SOC_RK3588,
  896. HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_RKVDEC | HAVE_RKVENC |
  897. HAVE_JPEG_DEC | HAVE_AV1DEC | HAVE_AVSDEC | HAVE_VEPU2_JPEG,
  898. { &vdpu38x, &rkjpegd, &vdpu2, &vdpu2_jpeg_pp_fix, &av1d, &avspd},
  899. { &vepu58x, &vepu2, &vepu2_jpeg_enhanced, NULL, },
  900. },
  901. { /*
  902. * rk3528 has codec:
  903. * 1 - vpu2 for jpeg/vp8 decoder
  904. * 2 - RK H.264/H.265 4K decoder
  905. * 3 - RK H.264/H.265 1080P encoder
  906. * 4 - RK jpeg decoder
  907. */
  908. "rk3528",
  909. ROCKCHIP_SOC_RK3528,
  910. HAVE_RKVDEC | HAVE_RKVENC | HAVE_VDPU2 | HAVE_JPEG_DEC | HAVE_AVSDEC,
  911. { &vdpu382, &rkjpegd, &vdpu2, &avspd, NULL, NULL, },
  912. { &vepu540c, NULL, NULL, NULL, },
  913. },
  914. { /*
  915. * rk3528a has codec:
  916. * 1 - vpu2 for jpeg/vp8 decoder
  917. * 2 - RK H.264/H.265/VP9 4K decoder
  918. * 3 - RK H.264/H.265 1080P encoder
  919. * 4 - RK jpeg decoder
  920. */
  921. "rk3528a",
  922. ROCKCHIP_SOC_RK3528,
  923. HAVE_RKVDEC | HAVE_RKVENC | HAVE_VDPU2 | HAVE_JPEG_DEC | HAVE_AVSDEC,
  924. { &vdpu382a, &rkjpegd, &vdpu2, &avspd, NULL, NULL, },
  925. { &vepu540c, NULL, NULL, NULL, },
  926. },
  927. { /*
  928. * rk3562 has codec:
  929. * 1 - RK H.264/H.265/VP9 4K decoder
  930. * 2 - RK H.264 1080P encoder
  931. * 3 - RK jpeg decoder
  932. */
  933. "rk3562",
  934. ROCKCHIP_SOC_RK3562,
  935. HAVE_RKVDEC | HAVE_RKVENC | HAVE_JPEG_DEC,
  936. { &vdpu382_lite, &rkjpegd, NULL, NULL, NULL, NULL, },
  937. { &vepu540c_no_hevc, NULL, NULL, NULL, },
  938. },
  939. { /*
  940. * rk3576 has codec:
  941. * 1 - RK H.264/H.265/VP9/AVS2/AV1 8K decoder
  942. * 2 - RK H.264/H.265 8K encoder
  943. * 3 - RK jpeg decoder/encoder
  944. */
  945. "rk3576",
  946. ROCKCHIP_SOC_RK3576,
  947. HAVE_RKVDEC | HAVE_RKVENC | HAVE_JPEG_DEC | HAVE_JPEG_ENC,
  948. { &vdpu383, &rkjpegd, NULL, NULL, NULL, NULL},
  949. { &vepu510, &rkjpege_vpu720, NULL, NULL},
  950. },
  951. { /*
  952. * rv1126b has codec:
  953. * 1 - RK H.264/H.265 4K decoder
  954. * 2 - RK H.264/H.265/jpeg 4K encoder
  955. * 3 - RK jpeg decoder
  956. */
  957. "rv1126b",
  958. ROCKCHIP_SOC_RV1126B,
  959. HAVE_RKVDEC | HAVE_RKVENC | HAVE_JPEG_DEC,
  960. { &vdpu384a, &rkjpegd, NULL, NULL, NULL, NULL},
  961. { &vepu511, NULL, NULL, NULL},
  962. },
  963. };
  964. static const MppSocInfo mpp_soc_default = {
  965. "unknown",
  966. ROCKCHIP_SOC_AUTO,
  967. HAVE_VDPU2 | HAVE_VEPU2 | HAVE_VDPU1 | HAVE_VEPU1,
  968. { &vdpu2, &vdpu1, NULL, NULL, },
  969. { &vepu2, &vepu1, NULL, NULL, },
  970. };
  971. static void read_soc_name(char *name, RK_S32 size)
  972. {
  973. const char *path = "/proc/device-tree/compatible";
  974. RK_S32 fd = open(path, O_RDONLY);
  975. if (fd < 0) {
  976. mpp_err("open %s error\n", path);
  977. } else {
  978. ssize_t soc_name_len = 0;
  979. snprintf(name, size - 1, "unknown");
  980. soc_name_len = read(fd, name, size - 1);
  981. if (soc_name_len > 0) {
  982. name[soc_name_len] = '\0';
  983. /* replacing the termination character to space */
  984. for (char *ptr = name;; ptr = name) {
  985. ptr += strnlen(name, size);
  986. if (ptr >= name + soc_name_len - 1)
  987. break;
  988. *ptr = ' ';
  989. }
  990. mpp_dbg_platform("chip name: %s\n", name);
  991. }
  992. close(fd);
  993. }
  994. }
  995. static const MppSocInfo *check_soc_info(const char *soc_name)
  996. {
  997. RK_S32 i;
  998. for (i = MPP_ARRAY_ELEMS(mpp_soc_infos) - 1; i >= 0; i--) {
  999. const char *compatible = mpp_soc_infos[i].compatible;
  1000. if (strstr(soc_name, compatible)) {
  1001. mpp_dbg_platform("match chip name: %s\n", compatible);
  1002. return &mpp_soc_infos[i];
  1003. }
  1004. }
  1005. return NULL;
  1006. }
  1007. class MppSocService
  1008. {
  1009. private:
  1010. // avoid any unwanted function
  1011. MppSocService();
  1012. ~MppSocService() {};
  1013. MppSocService(const MppSocService &);
  1014. MppSocService &operator=(const MppSocService &);
  1015. char soc_name[MAX_SOC_NAME_LENGTH];
  1016. const MppSocInfo *soc_info;
  1017. RK_U32 dec_coding_cap;
  1018. RK_U32 enc_coding_cap;
  1019. public:
  1020. static MppSocService *get() {
  1021. static MppSocService instance;
  1022. return &instance;
  1023. }
  1024. const char *get_soc_name() { return soc_name; };
  1025. const MppSocInfo *get_soc_info() { return soc_info; };
  1026. RK_U32 get_dec_cap() { return dec_coding_cap; };
  1027. RK_U32 get_enc_cap() { return enc_coding_cap; };
  1028. };
  1029. MppSocService::MppSocService()
  1030. : soc_info(NULL),
  1031. dec_coding_cap(0),
  1032. enc_coding_cap(0)
  1033. {
  1034. RK_U32 i;
  1035. RK_U32 vcodec_type = 0;
  1036. read_soc_name(soc_name, sizeof(soc_name));
  1037. soc_info = check_soc_info(soc_name);
  1038. if (NULL == soc_info) {
  1039. mpp_dbg_platform("use default chip info\n");
  1040. soc_info = &mpp_soc_default;
  1041. }
  1042. for (i = 0; i < MPP_ARRAY_ELEMS(soc_info->dec_caps); i++) {
  1043. const MppDecHwCap *cap = soc_info->dec_caps[i];
  1044. if (cap && cap->cap_coding) {
  1045. dec_coding_cap |= cap->cap_coding;
  1046. vcodec_type |= (1 << cap->type);
  1047. }
  1048. }
  1049. for (i = 0; i < MPP_ARRAY_ELEMS(soc_info->enc_caps); i++) {
  1050. const MppEncHwCap *cap = soc_info->enc_caps[i];
  1051. if (cap && cap->cap_coding) {
  1052. enc_coding_cap |= cap->cap_coding;
  1053. vcodec_type |= (1 << cap->type);
  1054. }
  1055. }
  1056. mpp_dbg_platform("coding caps: dec %08x enc %08x\n",
  1057. dec_coding_cap, enc_coding_cap);
  1058. mpp_dbg_platform("vcodec type from cap: %08x, from soc_info %08x\n",
  1059. vcodec_type, soc_info->vcodec_type);
  1060. mpp_assert(soc_info->vcodec_type == vcodec_type);
  1061. }
  1062. const char *mpp_get_soc_name(void)
  1063. {
  1064. static const char *soc_name = NULL;
  1065. if (soc_name)
  1066. return soc_name;
  1067. soc_name = MppSocService::get()->get_soc_name();
  1068. return soc_name;
  1069. }
  1070. const MppSocInfo *mpp_get_soc_info(void)
  1071. {
  1072. static const MppSocInfo *soc_info = NULL;
  1073. if (soc_info)
  1074. return soc_info;
  1075. soc_info = MppSocService::get()->get_soc_info();
  1076. return soc_info;
  1077. }
  1078. RockchipSocType mpp_get_soc_type(void)
  1079. {
  1080. static RockchipSocType soc_type = ROCKCHIP_SOC_AUTO;
  1081. if (soc_type)
  1082. return soc_type;
  1083. soc_type = MppSocService::get()->get_soc_info()->soc_type;
  1084. return soc_type;
  1085. }
  1086. static RK_U32 is_valid_cap_coding(RK_U32 cap, MppCodingType coding)
  1087. {
  1088. RK_S32 index = CODING_TO_IDX(coding);
  1089. if (index > 0 && index < 32 && (cap & (RK_U32)(1 << index)))
  1090. return true;
  1091. return false;
  1092. }
  1093. RK_U32 mpp_check_soc_cap(MppCtxType type, MppCodingType coding)
  1094. {
  1095. RK_U32 cap = 0;
  1096. if (type == MPP_CTX_DEC)
  1097. cap = MppSocService::get()->get_dec_cap();
  1098. else if (type == MPP_CTX_ENC)
  1099. cap = MppSocService::get()->get_enc_cap();
  1100. else
  1101. return 0;
  1102. if (!cap)
  1103. return 0;
  1104. return is_valid_cap_coding(cap, coding);
  1105. }
  1106. const MppDecHwCap* mpp_get_dec_hw_info_by_client_type(MppClientType client_type)
  1107. {
  1108. const MppDecHwCap* hw_info = NULL;
  1109. const MppSocInfo *info = mpp_get_soc_info();
  1110. RK_U32 i = 0;
  1111. for (i = 0; i < MPP_ARRAY_ELEMS(info->dec_caps); i++) {
  1112. if (info->dec_caps[i] && info->dec_caps[i]->type == client_type) {
  1113. hw_info = info->dec_caps[i];
  1114. break;
  1115. }
  1116. }
  1117. return hw_info;
  1118. }