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davinci_nand.h

davinci_nand.h 2.3 KB
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  1. /*
    2. 

  2.  * NAND Flash Driver
    3. 

  3.  *
    4. 

  4.  * Copyright (C) 2006-2014 Texas Instruments.
    5. 

  5.  *
    6. 

  6.  * Based on Linux DaVinci NAND driver by TI.
    7. 

  7.  */
    8. 

  8. 

  9. #ifndef _DAVINCI_NAND_H_
    10. 

  10. #define _DAVINCI_NAND_H_
    11. 

  11. 

  12. #include <linux/mtd/nand.h>
    13. 

  13. #include <asm/arch/hardware.h>
    14. 

  14. 

  15. #define NAND_READ_START  	0x00
    16. 

  16. #define NAND_READ_END    	0x30
    17. 

  17. #define NAND_STATUS      	0x70
    18. 

  18. 

  19. #define MASK_CLE		0x10
    20. 

  20. #define MASK_ALE		0x08
    21. 

  21. 

  22. #ifdef CONFIG_SYS_NAND_MASK_CLE
    23. 

  23. #undef MASK_CLE
    24. 

  24. #define MASK_CLE CONFIG_SYS_NAND_MASK_CLE
    25. 

  25. #endif
    26. 

  26. #ifdef CONFIG_SYS_NAND_MASK_ALE
    27. 

  27. #undef MASK_ALE
    28. 

  28. #define MASK_ALE CONFIG_SYS_NAND_MASK_ALE
    29. 

  29. #endif
    30. 

  30. 

  31. struct davinci_emif_regs {
    32. 

  32. 	uint32_t	ercsr;
    33. 

  33. 	uint32_t	awccr;
    34. 

  34. 	uint32_t	sdbcr;
    35. 

  35. 	uint32_t	sdrcr;
    36. 

  36. 	union {
    37. 

  37. 		uint32_t abncr[4];
    38. 

  38. 		uint32_t ab1cr;
    39. 

  39. 		uint32_t ab2cr;
    40. 

  40. 		uint32_t ab3cr;
    41. 

  41. 		uint32_t ab4cr;
    42. 

  42. 	};
    43. 

  43. 	uint32_t	sdtimr;
    44. 

  44. 	uint32_t	ddrsr;
    45. 

  45. 	uint32_t	ddrphycr;
    46. 

  46. 	uint32_t	ddrphysr;
    47. 

  47. 	uint32_t	totar;
    48. 

  48. 	uint32_t	totactr;
    49. 

  49. 	uint32_t	ddrphyid_rev;
    50. 

  50. 	uint32_t	sdsretr;
    51. 

  51. 	uint32_t	eirr;
    52. 

  52. 	uint32_t	eimr;
    53. 

  53. 	uint32_t	eimsr;
    54. 

  54. 	uint32_t	eimcr;
    55. 

  55. 	uint32_t	ioctrlr;
    56. 

  56. 	uint32_t	iostatr;
    57. 

  57. 	uint32_t	rsvd0;
    58. 

  58. 	uint32_t	one_nand_cr;
    59. 

  59. 	uint32_t	nandfcr;
    60. 

  60. 	uint32_t	nandfsr;
    61. 

  61. 	uint32_t	rsvd1[2];
    62. 

  62. 	uint32_t	nandfecc[4];
    63. 

  63. 	uint32_t	rsvd2[15];
    64. 

  64. 	uint32_t	nand4biteccload;
    65. 

  65. 	uint32_t	nand4bitecc[4];
    66. 

  66. 	uint32_t	nanderradd1;
    67. 

  67. 	uint32_t	nanderradd2;
    68. 

  68. 	uint32_t	nanderrval1;
    69. 

  69. 	uint32_t	nanderrval2;
    70. 

  70. };
    71. 

  71. 

  72. #define davinci_emif_regs \
    73. 

  73. 	((struct davinci_emif_regs *)DAVINCI_ASYNC_EMIF_CNTRL_BASE)
    74. 

  74. 

  75. #define DAVINCI_NANDFCR_NAND_ENABLE(n)			(1 << ((n) - 2))
    76. 

  76. #define DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK		(3 << 4)
    77. 

  77. #define DAVINCI_NANDFCR_4BIT_ECC_SEL(n)			(((n) - 2) << 4)
    78. 

  78. #define DAVINCI_NANDFCR_1BIT_ECC_START(n)		(1 << (8 + ((n) - 2)))
    79. 

  79. #define DAVINCI_NANDFCR_4BIT_ECC_START			(1 << 12)
    80. 

  80. #define DAVINCI_NANDFCR_4BIT_CALC_START			(1 << 13)
    81. 

  81. #define DAVINCI_NANDFCR_CS2NAND				(1 << 0)
    82. 

  82. 

  83. /* Chip Select setup */
    84. 

  84. #define DAVINCI_ABCR_STROBE_SELECT			(1 << 31)
    85. 

  85. #define DAVINCI_ABCR_EXT_WAIT				(1 << 30)
    86. 

  86. #define DAVINCI_ABCR_WSETUP(n)				(n << 26)
    87. 

  87. #define DAVINCI_ABCR_WSTROBE(n)				(n << 20)
    88. 

  88. #define DAVINCI_ABCR_WHOLD(n)				(n << 17)
    89. 

  89. #define DAVINCI_ABCR_RSETUP(n)				(n << 13)
    90. 

  90. #define DAVINCI_ABCR_RSTROBE(n)				(n << 7)
    91. 

  91. #define DAVINCI_ABCR_RHOLD(n)				(n << 4)
    92. 

  92. #define DAVINCI_ABCR_TA(n)				(n << 2)
    93. 

  93. #define DAVINCI_ABCR_ASIZE_16BIT			1
    94. 

  94. #define DAVINCI_ABCR_ASIZE_8BIT				0
    95. 

  95. 

  96. void davinci_nand_init(struct nand_chip *nand);
    97. 

  97. 

  98. #endif
    99.