ddr.c 7.4 KB

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  1. /*
  2. * DDR Configuration for AM33xx devices.
  3. *
  4. * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
  5. *
  6. * SPDX-License-Identifier: GPL-2.0+
  7. */
  8. #include <asm/arch/cpu.h>
  9. #include <asm/arch/ddr_defs.h>
  10. #include <asm/arch/sys_proto.h>
  11. #include <asm/io.h>
  12. #include <asm/emif.h>
  13. /**
  14. * Base address for EMIF instances
  15. */
  16. static struct emif_reg_struct *emif_reg[2] = {
  17. (struct emif_reg_struct *)EMIF4_0_CFG_BASE,
  18. (struct emif_reg_struct *)EMIF4_1_CFG_BASE};
  19. /**
  20. * Base addresses for DDR PHY cmd/data regs
  21. */
  22. static struct ddr_cmd_regs *ddr_cmd_reg[2] = {
  23. (struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR,
  24. (struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR2};
  25. static struct ddr_data_regs *ddr_data_reg[2] = {
  26. (struct ddr_data_regs *)DDR_PHY_DATA_ADDR,
  27. (struct ddr_data_regs *)DDR_PHY_DATA_ADDR2};
  28. /**
  29. * Base address for ddr io control instances
  30. */
  31. static struct ddr_cmdtctrl *ioctrl_reg = {
  32. (struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR};
  33. static inline u32 get_mr(int nr, u32 cs, u32 mr_addr)
  34. {
  35. u32 mr;
  36. mr_addr |= cs << EMIF_REG_CS_SHIFT;
  37. writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg);
  38. mr = readl(&emif_reg[nr]->emif_lpddr2_mode_reg_data);
  39. debug("get_mr: EMIF1 cs %d mr %08x val 0x%x\n", cs, mr_addr, mr);
  40. if (((mr & 0x0000ff00) >> 8) == (mr & 0xff) &&
  41. ((mr & 0x00ff0000) >> 16) == (mr & 0xff) &&
  42. ((mr & 0xff000000) >> 24) == (mr & 0xff))
  43. return mr & 0xff;
  44. else
  45. return mr;
  46. }
  47. static inline void set_mr(int nr, u32 cs, u32 mr_addr, u32 mr_val)
  48. {
  49. mr_addr |= cs << EMIF_REG_CS_SHIFT;
  50. writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg);
  51. writel(mr_val, &emif_reg[nr]->emif_lpddr2_mode_reg_data);
  52. }
  53. static void configure_mr(int nr, u32 cs)
  54. {
  55. u32 mr_addr;
  56. while (get_mr(nr, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK)
  57. ;
  58. set_mr(nr, cs, LPDDR2_MR10, 0x56);
  59. set_mr(nr, cs, LPDDR2_MR1, 0x43);
  60. set_mr(nr, cs, LPDDR2_MR2, 0x2);
  61. mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK;
  62. set_mr(nr, cs, mr_addr, 0x2);
  63. }
  64. /*
  65. * Configure EMIF4D5 registers and MR registers
  66. */
  67. void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
  68. {
  69. writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl);
  70. writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl_shdw);
  71. writel(0x1, &emif_reg[nr]->emif_iodft_tlgc);
  72. writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
  73. writel(regs->temp_alert_config, &emif_reg[nr]->emif_temp_alert_config);
  74. writel(regs->emif_rd_wr_lvl_rmp_win,
  75. &emif_reg[nr]->emif_rd_wr_lvl_rmp_win);
  76. writel(regs->emif_rd_wr_lvl_rmp_ctl,
  77. &emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl);
  78. writel(regs->emif_rd_wr_lvl_ctl, &emif_reg[nr]->emif_rd_wr_lvl_ctl);
  79. writel(regs->emif_rd_wr_exec_thresh,
  80. &emif_reg[nr]->emif_rd_wr_exec_thresh);
  81. writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
  82. writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
  83. writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
  84. writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
  85. if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2) {
  86. configure_mr(nr, 0);
  87. configure_mr(nr, 1);
  88. }
  89. }
  90. /**
  91. * Configure SDRAM
  92. */
  93. void config_sdram(const struct emif_regs *regs, int nr)
  94. {
  95. if (regs->zq_config) {
  96. /*
  97. * A value of 0x2800 for the REF CTRL will give us
  98. * about 570us for a delay, which will be long enough
  99. * to configure things.
  100. */
  101. writel(0x2800, &emif_reg[nr]->emif_sdram_ref_ctrl);
  102. writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
  103. writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
  104. writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
  105. writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
  106. writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
  107. }
  108. writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
  109. writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
  110. writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
  111. }
  112. /**
  113. * Set SDRAM timings
  114. */
  115. void set_sdram_timings(const struct emif_regs *regs, int nr)
  116. {
  117. writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1);
  118. writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1_shdw);
  119. writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2);
  120. writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2_shdw);
  121. writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3);
  122. writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3_shdw);
  123. }
  124. void __weak emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
  125. {
  126. }
  127. /*
  128. * Configure EXT PHY registers
  129. */
  130. static void ext_phy_settings(const struct emif_regs *regs, int nr)
  131. {
  132. u32 *ext_phy_ctrl_base = 0;
  133. u32 *emif_ext_phy_ctrl_base = 0;
  134. const u32 *ext_phy_ctrl_const_regs;
  135. u32 i = 0;
  136. u32 size;
  137. ext_phy_ctrl_base = (u32 *)&(regs->emif_ddr_ext_phy_ctrl_1);
  138. emif_ext_phy_ctrl_base =
  139. (u32 *)&(emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);
  140. /* Configure external phy control timing registers */
  141. for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
  142. writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
  143. /* Update shadow registers */
  144. writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
  145. }
  146. /*
  147. * external phy 6-24 registers do not change with
  148. * ddr frequency
  149. */
  150. emif_get_ext_phy_ctrl_const_regs(&ext_phy_ctrl_const_regs, &size);
  151. if (!size)
  152. return;
  153. for (i = 0; i < size; i++) {
  154. writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++);
  155. /* Update shadow registers */
  156. writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++);
  157. }
  158. }
  159. /**
  160. * Configure DDR PHY
  161. */
  162. void config_ddr_phy(const struct emif_regs *regs, int nr)
  163. {
  164. /*
  165. * disable initialization and refreshes for now until we
  166. * finish programming EMIF regs.
  167. */
  168. setbits_le32(&emif_reg[nr]->emif_sdram_ref_ctrl,
  169. EMIF_REG_INITREF_DIS_MASK);
  170. writel(regs->emif_ddr_phy_ctlr_1,
  171. &emif_reg[nr]->emif_ddr_phy_ctrl_1);
  172. writel(regs->emif_ddr_phy_ctlr_1,
  173. &emif_reg[nr]->emif_ddr_phy_ctrl_1_shdw);
  174. if (get_emif_rev((u32)emif_reg[nr]) == EMIF_4D5)
  175. ext_phy_settings(regs, nr);
  176. }
  177. /**
  178. * Configure DDR CMD control registers
  179. */
  180. void config_cmd_ctrl(const struct cmd_control *cmd, int nr)
  181. {
  182. if (!cmd)
  183. return;
  184. writel(cmd->cmd0csratio, &ddr_cmd_reg[nr]->cm0csratio);
  185. writel(cmd->cmd0iclkout, &ddr_cmd_reg[nr]->cm0iclkout);
  186. writel(cmd->cmd1csratio, &ddr_cmd_reg[nr]->cm1csratio);
  187. writel(cmd->cmd1iclkout, &ddr_cmd_reg[nr]->cm1iclkout);
  188. writel(cmd->cmd2csratio, &ddr_cmd_reg[nr]->cm2csratio);
  189. writel(cmd->cmd2iclkout, &ddr_cmd_reg[nr]->cm2iclkout);
  190. }
  191. /**
  192. * Configure DDR DATA registers
  193. */
  194. void config_ddr_data(const struct ddr_data *data, int nr)
  195. {
  196. int i;
  197. if (!data)
  198. return;
  199. for (i = 0; i < DDR_DATA_REGS_NR; i++) {
  200. writel(data->datardsratio0,
  201. &(ddr_data_reg[nr]+i)->dt0rdsratio0);
  202. writel(data->datawdsratio0,
  203. &(ddr_data_reg[nr]+i)->dt0wdsratio0);
  204. writel(data->datawiratio0,
  205. &(ddr_data_reg[nr]+i)->dt0wiratio0);
  206. writel(data->datagiratio0,
  207. &(ddr_data_reg[nr]+i)->dt0giratio0);
  208. writel(data->datafwsratio0,
  209. &(ddr_data_reg[nr]+i)->dt0fwsratio0);
  210. writel(data->datawrsratio0,
  211. &(ddr_data_reg[nr]+i)->dt0wrsratio0);
  212. }
  213. }
  214. void config_io_ctrl(const struct ctrl_ioregs *ioregs)
  215. {
  216. if (!ioregs)
  217. return;
  218. writel(ioregs->cm0ioctl, &ioctrl_reg->cm0ioctl);
  219. writel(ioregs->cm1ioctl, &ioctrl_reg->cm1ioctl);
  220. writel(ioregs->cm2ioctl, &ioctrl_reg->cm2ioctl);
  221. writel(ioregs->dt0ioctl, &ioctrl_reg->dt0ioctl);
  222. writel(ioregs->dt1ioctl, &ioctrl_reg->dt1ioctl);
  223. #ifdef CONFIG_AM43XX
  224. writel(ioregs->dt2ioctrl, &ioctrl_reg->dt2ioctrl);
  225. writel(ioregs->dt3ioctrl, &ioctrl_reg->dt3ioctrl);
  226. writel(ioregs->emif_sdram_config_ext,
  227. &ioctrl_reg->emif_sdram_config_ext);
  228. #endif
  229. }