threei.c 2.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2002
  4. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  5. */
  6. #include <common.h>
  7. /*
  8. * CPU test
  9. * Ternary instructions instr rA,rS,UIMM
  10. *
  11. * Logic instructions: ori, oris, xori, xoris
  12. *
  13. * The test contains a pre-built table of instructions, operands and
  14. * expected results. For each table entry, the test will cyclically use
  15. * different sets of operand registers and result registers.
  16. */
  17. #include <post.h>
  18. #include "cpu_asm.h"
  19. #if CONFIG_POST & CONFIG_SYS_POST_CPU
  20. extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op);
  21. extern ulong cpu_post_makecr (long v);
  22. static struct cpu_post_threei_s
  23. {
  24. ulong cmd;
  25. ulong op1;
  26. ushort op2;
  27. ulong res;
  28. } cpu_post_threei_table[] =
  29. {
  30. {
  31. OP_ORI,
  32. 0x80000000,
  33. 0xffff,
  34. 0x8000ffff
  35. },
  36. {
  37. OP_ORIS,
  38. 0x00008000,
  39. 0xffff,
  40. 0xffff8000
  41. },
  42. {
  43. OP_XORI,
  44. 0x8000ffff,
  45. 0xffff,
  46. 0x80000000
  47. },
  48. {
  49. OP_XORIS,
  50. 0x00008000,
  51. 0xffff,
  52. 0xffff8000
  53. },
  54. };
  55. static unsigned int cpu_post_threei_size = ARRAY_SIZE(cpu_post_threei_table);
  56. int cpu_post_test_threei (void)
  57. {
  58. int ret = 0;
  59. unsigned int i, reg;
  60. int flag = disable_interrupts();
  61. for (i = 0; i < cpu_post_threei_size && ret == 0; i++)
  62. {
  63. struct cpu_post_threei_s *test = cpu_post_threei_table + i;
  64. for (reg = 0; reg < 32 && ret == 0; reg++)
  65. {
  66. unsigned int reg0 = (reg + 0) % 32;
  67. unsigned int reg1 = (reg + 1) % 32;
  68. unsigned int stk = reg < 16 ? 31 : 15;
  69. unsigned long code[] =
  70. {
  71. ASM_STW(stk, 1, -4),
  72. ASM_ADDI(stk, 1, -16),
  73. ASM_STW(3, stk, 8),
  74. ASM_STW(reg0, stk, 4),
  75. ASM_STW(reg1, stk, 0),
  76. ASM_LWZ(reg0, stk, 8),
  77. ASM_11IX(test->cmd, reg1, reg0, test->op2),
  78. ASM_STW(reg1, stk, 8),
  79. ASM_LWZ(reg1, stk, 0),
  80. ASM_LWZ(reg0, stk, 4),
  81. ASM_LWZ(3, stk, 8),
  82. ASM_ADDI(1, stk, 16),
  83. ASM_LWZ(stk, 1, -4),
  84. ASM_BLR,
  85. };
  86. ulong res;
  87. ulong cr;
  88. cr = 0;
  89. cpu_post_exec_21 (code, & cr, & res, test->op1);
  90. ret = res == test->res && cr == 0 ? 0 : -1;
  91. if (ret != 0)
  92. {
  93. post_log ("Error at threei test %d !\n", i);
  94. }
  95. }
  96. }
  97. if (flag)
  98. enable_interrupts();
  99. return ret;
  100. }
  101. #endif