cpu.c 2.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2002
  4. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  5. */
  6. #include <common.h>
  7. /*
  8. * CPU test
  9. *
  10. * This test checks the arithmetic logic unit (ALU) of CPU.
  11. * It tests independently various groups of instructions using
  12. * run-time modification of the code to reduce the memory footprint.
  13. * For more details refer to post/cpu/ *.c files.
  14. */
  15. #include <watchdog.h>
  16. #include <post.h>
  17. #include <asm/mmu.h>
  18. #if CONFIG_POST & CONFIG_SYS_POST_CPU
  19. extern int cpu_post_test_cmp (void);
  20. extern int cpu_post_test_cmpi (void);
  21. extern int cpu_post_test_two (void);
  22. extern int cpu_post_test_twox (void);
  23. extern int cpu_post_test_three (void);
  24. extern int cpu_post_test_threex (void);
  25. extern int cpu_post_test_threei (void);
  26. extern int cpu_post_test_andi (void);
  27. extern int cpu_post_test_srawi (void);
  28. extern int cpu_post_test_rlwnm (void);
  29. extern int cpu_post_test_rlwinm (void);
  30. extern int cpu_post_test_rlwimi (void);
  31. extern int cpu_post_test_store (void);
  32. extern int cpu_post_test_load (void);
  33. extern int cpu_post_test_cr (void);
  34. extern int cpu_post_test_b (void);
  35. extern int cpu_post_test_multi (void);
  36. extern int cpu_post_test_string (void);
  37. extern int cpu_post_test_complex (void);
  38. ulong cpu_post_makecr (long v)
  39. {
  40. ulong cr = 0;
  41. if (v < 0)
  42. cr |= 0x80000000;
  43. if (v > 0)
  44. cr |= 0x40000000;
  45. if (v == 0)
  46. cr |= 0x20000000;
  47. return cr;
  48. }
  49. int cpu_post_test (int flags)
  50. {
  51. int ic = icache_status ();
  52. int ret = 0;
  53. WATCHDOG_RESET();
  54. if (ic)
  55. icache_disable ();
  56. if (ret == 0)
  57. ret = cpu_post_test_cmp ();
  58. if (ret == 0)
  59. ret = cpu_post_test_cmpi ();
  60. if (ret == 0)
  61. ret = cpu_post_test_two ();
  62. if (ret == 0)
  63. ret = cpu_post_test_twox ();
  64. WATCHDOG_RESET();
  65. if (ret == 0)
  66. ret = cpu_post_test_three ();
  67. if (ret == 0)
  68. ret = cpu_post_test_threex ();
  69. if (ret == 0)
  70. ret = cpu_post_test_threei ();
  71. if (ret == 0)
  72. ret = cpu_post_test_andi ();
  73. WATCHDOG_RESET();
  74. if (ret == 0)
  75. ret = cpu_post_test_srawi ();
  76. if (ret == 0)
  77. ret = cpu_post_test_rlwnm ();
  78. if (ret == 0)
  79. ret = cpu_post_test_rlwinm ();
  80. if (ret == 0)
  81. ret = cpu_post_test_rlwimi ();
  82. WATCHDOG_RESET();
  83. if (ret == 0)
  84. ret = cpu_post_test_store ();
  85. if (ret == 0)
  86. ret = cpu_post_test_load ();
  87. if (ret == 0)
  88. ret = cpu_post_test_cr ();
  89. if (ret == 0)
  90. ret = cpu_post_test_b ();
  91. WATCHDOG_RESET();
  92. if (ret == 0)
  93. ret = cpu_post_test_multi ();
  94. WATCHDOG_RESET();
  95. if (ret == 0)
  96. ret = cpu_post_test_string ();
  97. if (ret == 0)
  98. ret = cpu_post_test_complex ();
  99. WATCHDOG_RESET();
  100. if (ic)
  101. icache_enable ();
  102. WATCHDOG_RESET();
  103. return ret;
  104. }
  105. #endif /* CONFIG_POST & CONFIG_SYS_POST_CPU */