andi.c 2.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2002
  4. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  5. */
  6. #include <common.h>
  7. /*
  8. * CPU test
  9. * Logic instructions: andi., andis.
  10. *
  11. * The test contains a pre-built table of instructions, operands and
  12. * expected results. For each table entry, the test will cyclically use
  13. * different sets of operand registers and result registers.
  14. */
  15. #include <post.h>
  16. #include "cpu_asm.h"
  17. #if CONFIG_POST & CONFIG_SYS_POST_CPU
  18. extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op);
  19. extern ulong cpu_post_makecr (long v);
  20. static struct cpu_post_andi_s
  21. {
  22. ulong cmd;
  23. ulong op1;
  24. ushort op2;
  25. ulong res;
  26. } cpu_post_andi_table[] =
  27. {
  28. {
  29. OP_ANDI_,
  30. 0x80008000,
  31. 0xffff,
  32. 0x00008000
  33. },
  34. {
  35. OP_ANDIS_,
  36. 0x80008000,
  37. 0xffff,
  38. 0x80000000
  39. },
  40. };
  41. static unsigned int cpu_post_andi_size = ARRAY_SIZE(cpu_post_andi_table);
  42. int cpu_post_test_andi (void)
  43. {
  44. int ret = 0;
  45. unsigned int i, reg;
  46. int flag = disable_interrupts();
  47. for (i = 0; i < cpu_post_andi_size && ret == 0; i++)
  48. {
  49. struct cpu_post_andi_s *test = cpu_post_andi_table + i;
  50. for (reg = 0; reg < 32 && ret == 0; reg++)
  51. {
  52. unsigned int reg0 = (reg + 0) % 32;
  53. unsigned int reg1 = (reg + 1) % 32;
  54. unsigned int stk = reg < 16 ? 31 : 15;
  55. unsigned long codecr[] =
  56. {
  57. ASM_STW(stk, 1, -4),
  58. ASM_ADDI(stk, 1, -16),
  59. ASM_STW(3, stk, 8),
  60. ASM_STW(reg0, stk, 4),
  61. ASM_STW(reg1, stk, 0),
  62. ASM_LWZ(reg0, stk, 8),
  63. ASM_11IX(test->cmd, reg1, reg0, test->op2),
  64. ASM_STW(reg1, stk, 8),
  65. ASM_LWZ(reg1, stk, 0),
  66. ASM_LWZ(reg0, stk, 4),
  67. ASM_LWZ(3, stk, 8),
  68. ASM_ADDI(1, stk, 16),
  69. ASM_LWZ(stk, 1, -4),
  70. ASM_BLR,
  71. };
  72. ulong res;
  73. ulong cr;
  74. cpu_post_exec_21 (codecr, & cr, & res, test->op1);
  75. ret = res == test->res &&
  76. (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1;
  77. if (ret != 0)
  78. {
  79. post_log ("Error at andi test %d !\n", i);
  80. }
  81. }
  82. }
  83. if (flag)
  84. enable_interrupts();
  85. return ret;
  86. }
  87. #endif