sunxi_pwm.c 4.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2017-2018 Vasily Khoruzhick <anarsoul@gmail.com>
  4. */
  5. #include <common.h>
  6. #include <div64.h>
  7. #include <dm.h>
  8. #include <pwm.h>
  9. #include <regmap.h>
  10. #include <syscon.h>
  11. #include <asm/io.h>
  12. #include <asm/arch/pwm.h>
  13. #include <asm/arch/gpio.h>
  14. #include <power/regulator.h>
  15. DECLARE_GLOBAL_DATA_PTR;
  16. #define OSC_24MHZ 24000000
  17. struct sunxi_pwm_priv {
  18. struct sunxi_pwm *regs;
  19. bool invert;
  20. u32 prescaler;
  21. };
  22. static const u32 prescaler_table[] = {
  23. 120, /* 0000 */
  24. 180, /* 0001 */
  25. 240, /* 0010 */
  26. 360, /* 0011 */
  27. 480, /* 0100 */
  28. 0, /* 0101 */
  29. 0, /* 0110 */
  30. 0, /* 0111 */
  31. 12000, /* 1000 */
  32. 24000, /* 1001 */
  33. 36000, /* 1010 */
  34. 48000, /* 1011 */
  35. 72000, /* 1100 */
  36. 0, /* 1101 */
  37. 0, /* 1110 */
  38. 1, /* 1111 */
  39. };
  40. static int sunxi_pwm_config_pinmux(void)
  41. {
  42. #ifdef CONFIG_MACH_SUN50I
  43. sunxi_gpio_set_cfgpin(SUNXI_GPD(22), SUNXI_GPD_PWM);
  44. #endif
  45. return 0;
  46. }
  47. static int sunxi_pwm_set_invert(struct udevice *dev, uint channel,
  48. bool polarity)
  49. {
  50. struct sunxi_pwm_priv *priv = dev_get_priv(dev);
  51. debug("%s: polarity=%u\n", __func__, polarity);
  52. priv->invert = polarity;
  53. return 0;
  54. }
  55. static int sunxi_pwm_set_config(struct udevice *dev, uint channel,
  56. uint period_ns, uint duty_ns)
  57. {
  58. struct sunxi_pwm_priv *priv = dev_get_priv(dev);
  59. struct sunxi_pwm *regs = priv->regs;
  60. int best_prescaler = 0;
  61. u32 v, best_period = 0, duty;
  62. u64 best_scaled_freq = 0;
  63. const u32 nsecs_per_sec = 1000000000U;
  64. debug("%s: period_ns=%u, duty_ns=%u\n", __func__, period_ns, duty_ns);
  65. for (int prescaler = 0; prescaler <= SUNXI_PWM_CTRL_PRESCALE0_MASK;
  66. prescaler++) {
  67. u32 period = 0;
  68. u64 scaled_freq = 0;
  69. if (!prescaler_table[prescaler])
  70. continue;
  71. scaled_freq = lldiv(OSC_24MHZ, prescaler_table[prescaler]);
  72. period = lldiv(scaled_freq * period_ns, nsecs_per_sec);
  73. if ((period - 1 <= SUNXI_PWM_CH0_PERIOD_MAX) &&
  74. best_period < period) {
  75. best_period = period;
  76. best_scaled_freq = scaled_freq;
  77. best_prescaler = prescaler;
  78. }
  79. }
  80. if (best_period - 1 > SUNXI_PWM_CH0_PERIOD_MAX) {
  81. debug("%s: failed to find prescaler value\n", __func__);
  82. return -EINVAL;
  83. }
  84. duty = lldiv(best_scaled_freq * duty_ns, nsecs_per_sec);
  85. if (priv->prescaler != best_prescaler) {
  86. /* Mask clock to update prescaler */
  87. v = readl(&regs->ctrl);
  88. v &= ~SUNXI_PWM_CTRL_CLK_GATE;
  89. writel(v, &regs->ctrl);
  90. v &= ~SUNXI_PWM_CTRL_PRESCALE0_MASK;
  91. v |= (best_prescaler & SUNXI_PWM_CTRL_PRESCALE0_MASK);
  92. writel(v, &regs->ctrl);
  93. v |= SUNXI_PWM_CTRL_CLK_GATE;
  94. writel(v, &regs->ctrl);
  95. priv->prescaler = best_prescaler;
  96. }
  97. writel(SUNXI_PWM_CH0_PERIOD_PRD(best_period) |
  98. SUNXI_PWM_CH0_PERIOD_DUTY(duty), &regs->ch0_period);
  99. debug("%s: prescaler: %d, period: %d, duty: %d\n",
  100. __func__, priv->prescaler,
  101. best_period, duty);
  102. return 0;
  103. }
  104. static int sunxi_pwm_set_enable(struct udevice *dev, uint channel, bool enable)
  105. {
  106. struct sunxi_pwm_priv *priv = dev_get_priv(dev);
  107. struct sunxi_pwm *regs = priv->regs;
  108. u32 v;
  109. debug("%s: Enable '%s'\n", __func__, dev->name);
  110. v = readl(&regs->ctrl);
  111. if (!enable) {
  112. v &= ~SUNXI_PWM_CTRL_ENABLE0;
  113. writel(v, &regs->ctrl);
  114. return 0;
  115. }
  116. sunxi_pwm_config_pinmux();
  117. if (priv->invert)
  118. v &= ~SUNXI_PWM_CTRL_CH0_ACT_STA;
  119. else
  120. v |= SUNXI_PWM_CTRL_CH0_ACT_STA;
  121. v |= SUNXI_PWM_CTRL_ENABLE0;
  122. writel(v, &regs->ctrl);
  123. return 0;
  124. }
  125. static int sunxi_pwm_ofdata_to_platdata(struct udevice *dev)
  126. {
  127. struct sunxi_pwm_priv *priv = dev_get_priv(dev);
  128. priv->regs = (struct sunxi_pwm *)devfdt_get_addr(dev);
  129. return 0;
  130. }
  131. static int sunxi_pwm_probe(struct udevice *dev)
  132. {
  133. return 0;
  134. }
  135. static const struct pwm_ops sunxi_pwm_ops = {
  136. .set_invert = sunxi_pwm_set_invert,
  137. .set_config = sunxi_pwm_set_config,
  138. .set_enable = sunxi_pwm_set_enable,
  139. };
  140. static const struct udevice_id sunxi_pwm_ids[] = {
  141. { .compatible = "allwinner,sun5i-a13-pwm" },
  142. { .compatible = "allwinner,sun50i-a64-pwm" },
  143. { }
  144. };
  145. U_BOOT_DRIVER(sunxi_pwm) = {
  146. .name = "sunxi_pwm",
  147. .id = UCLASS_PWM,
  148. .of_match = sunxi_pwm_ids,
  149. .ops = &sunxi_pwm_ops,
  150. .ofdata_to_platdata = sunxi_pwm_ofdata_to_platdata,
  151. .probe = sunxi_pwm_probe,
  152. .priv_auto_alloc_size = sizeof(struct sunxi_pwm_priv),
  153. };