pcie_ecam_generic.c 4.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Generic PCIE host provided by e.g. QEMU
  4. *
  5. * Heavily based on drivers/pci/pcie_xilinx.c
  6. *
  7. * Copyright (C) 2016 Imagination Technologies
  8. */
  9. #include <common.h>
  10. #include <dm.h>
  11. #include <pci.h>
  12. #include <asm/io.h>
  13. /**
  14. * struct generic_ecam_pcie - generic_ecam PCIe controller state
  15. * @cfg_base: The base address of memory mapped configuration space
  16. */
  17. struct generic_ecam_pcie {
  18. void *cfg_base;
  19. };
  20. /**
  21. * pci_generic_ecam_conf_address() - Calculate the address of a config access
  22. * @bus: Pointer to the PCI bus
  23. * @bdf: Identifies the PCIe device to access
  24. * @offset: The offset into the device's configuration space
  25. * @paddress: Pointer to the pointer to write the calculates address to
  26. *
  27. * Calculates the address that should be accessed to perform a PCIe
  28. * configuration space access for a given device identified by the PCIe
  29. * controller device @pcie and the bus, device & function numbers in @bdf. If
  30. * access to the device is not valid then the function will return an error
  31. * code. Otherwise the address to access will be written to the pointer pointed
  32. * to by @paddress.
  33. */
  34. static int pci_generic_ecam_conf_address(struct udevice *bus, pci_dev_t bdf,
  35. uint offset, void **paddress)
  36. {
  37. struct generic_ecam_pcie *pcie = dev_get_priv(bus);
  38. void *addr;
  39. addr = pcie->cfg_base;
  40. addr += PCI_BUS(bdf) << 20;
  41. addr += PCI_DEV(bdf) << 15;
  42. addr += PCI_FUNC(bdf) << 12;
  43. addr += offset;
  44. *paddress = addr;
  45. return 0;
  46. }
  47. /**
  48. * pci_generic_ecam_read_config() - Read from configuration space
  49. * @bus: Pointer to the PCI bus
  50. * @bdf: Identifies the PCIe device to access
  51. * @offset: The offset into the device's configuration space
  52. * @valuep: A pointer at which to store the read value
  53. * @size: Indicates the size of access to perform
  54. *
  55. * Read a value of size @size from offset @offset within the configuration
  56. * space of the device identified by the bus, device & function numbers in @bdf
  57. * on the PCI bus @bus.
  58. */
  59. static int pci_generic_ecam_read_config(struct udevice *bus, pci_dev_t bdf,
  60. uint offset, ulong *valuep,
  61. enum pci_size_t size)
  62. {
  63. return pci_generic_mmap_read_config(bus, pci_generic_ecam_conf_address,
  64. bdf, offset, valuep, size);
  65. }
  66. /**
  67. * pci_generic_ecam_write_config() - Write to configuration space
  68. * @bus: Pointer to the PCI bus
  69. * @bdf: Identifies the PCIe device to access
  70. * @offset: The offset into the device's configuration space
  71. * @value: The value to write
  72. * @size: Indicates the size of access to perform
  73. *
  74. * Write the value @value of size @size from offset @offset within the
  75. * configuration space of the device identified by the bus, device & function
  76. * numbers in @bdf on the PCI bus @bus.
  77. */
  78. static int pci_generic_ecam_write_config(struct udevice *bus, pci_dev_t bdf,
  79. uint offset, ulong value,
  80. enum pci_size_t size)
  81. {
  82. return pci_generic_mmap_write_config(bus, pci_generic_ecam_conf_address,
  83. bdf, offset, value, size);
  84. }
  85. /**
  86. * pci_generic_ecam_ofdata_to_platdata() - Translate from DT to device state
  87. * @dev: A pointer to the device being operated on
  88. *
  89. * Translate relevant data from the device tree pertaining to device @dev into
  90. * state that the driver will later make use of. This state is stored in the
  91. * device's private data structure.
  92. *
  93. * Return: 0 on success, else -EINVAL
  94. */
  95. static int pci_generic_ecam_ofdata_to_platdata(struct udevice *dev)
  96. {
  97. struct generic_ecam_pcie *pcie = dev_get_priv(dev);
  98. struct fdt_resource reg_res;
  99. DECLARE_GLOBAL_DATA_PTR;
  100. int err;
  101. err = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev), "reg",
  102. 0, &reg_res);
  103. if (err < 0) {
  104. pr_err("\"reg\" resource not found\n");
  105. return err;
  106. }
  107. pcie->cfg_base = map_physmem(reg_res.start,
  108. fdt_resource_size(&reg_res),
  109. MAP_NOCACHE);
  110. return 0;
  111. }
  112. static const struct dm_pci_ops pci_generic_ecam_ops = {
  113. .read_config = pci_generic_ecam_read_config,
  114. .write_config = pci_generic_ecam_write_config,
  115. };
  116. static const struct udevice_id pci_generic_ecam_ids[] = {
  117. { .compatible = "pci-host-ecam-generic" },
  118. { }
  119. };
  120. U_BOOT_DRIVER(pci_generic_ecam) = {
  121. .name = "pci_generic_ecam",
  122. .id = UCLASS_PCI,
  123. .of_match = pci_generic_ecam_ids,
  124. .ops = &pci_generic_ecam_ops,
  125. .ofdata_to_platdata = pci_generic_ecam_ofdata_to_platdata,
  126. .priv_auto_alloc_size = sizeof(struct generic_ecam_pcie),
  127. };