pci_common.c 8.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2014 Google, Inc
  4. *
  5. * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  6. * Andreas Heppel <aheppel@sysgo.de>
  7. *
  8. * (C) Copyright 2002, 2003
  9. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  10. */
  11. #include <common.h>
  12. #include <dm.h>
  13. #include <errno.h>
  14. #include <pci.h>
  15. #include <asm/io.h>
  16. const char *pci_class_str(u8 class)
  17. {
  18. switch (class) {
  19. case PCI_CLASS_NOT_DEFINED:
  20. return "Build before PCI Rev2.0";
  21. break;
  22. case PCI_BASE_CLASS_STORAGE:
  23. return "Mass storage controller";
  24. break;
  25. case PCI_BASE_CLASS_NETWORK:
  26. return "Network controller";
  27. break;
  28. case PCI_BASE_CLASS_DISPLAY:
  29. return "Display controller";
  30. break;
  31. case PCI_BASE_CLASS_MULTIMEDIA:
  32. return "Multimedia device";
  33. break;
  34. case PCI_BASE_CLASS_MEMORY:
  35. return "Memory controller";
  36. break;
  37. case PCI_BASE_CLASS_BRIDGE:
  38. return "Bridge device";
  39. break;
  40. case PCI_BASE_CLASS_COMMUNICATION:
  41. return "Simple comm. controller";
  42. break;
  43. case PCI_BASE_CLASS_SYSTEM:
  44. return "Base system peripheral";
  45. break;
  46. case PCI_BASE_CLASS_INPUT:
  47. return "Input device";
  48. break;
  49. case PCI_BASE_CLASS_DOCKING:
  50. return "Docking station";
  51. break;
  52. case PCI_BASE_CLASS_PROCESSOR:
  53. return "Processor";
  54. break;
  55. case PCI_BASE_CLASS_SERIAL:
  56. return "Serial bus controller";
  57. break;
  58. case PCI_BASE_CLASS_INTELLIGENT:
  59. return "Intelligent controller";
  60. break;
  61. case PCI_BASE_CLASS_SATELLITE:
  62. return "Satellite controller";
  63. break;
  64. case PCI_BASE_CLASS_CRYPT:
  65. return "Cryptographic device";
  66. break;
  67. case PCI_BASE_CLASS_SIGNAL_PROCESSING:
  68. return "DSP";
  69. break;
  70. case PCI_CLASS_OTHERS:
  71. return "Does not fit any class";
  72. break;
  73. default:
  74. return "???";
  75. break;
  76. };
  77. }
  78. __weak int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
  79. {
  80. /*
  81. * Check if pci device should be skipped in configuration
  82. */
  83. if (dev == PCI_BDF(hose->first_busno, 0, 0)) {
  84. #if defined(CONFIG_PCI_CONFIG_HOST_BRIDGE) /* don't skip host bridge */
  85. /*
  86. * Only skip configuration if "pciconfighost" is not set
  87. */
  88. if (env_get("pciconfighost") == NULL)
  89. return 1;
  90. #else
  91. return 1;
  92. #endif
  93. }
  94. return 0;
  95. }
  96. #if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT)
  97. /* Get a virtual address associated with a BAR region */
  98. void *pci_map_bar(pci_dev_t pdev, int bar, int flags)
  99. {
  100. pci_addr_t pci_bus_addr;
  101. u32 bar_response;
  102. /* read BAR address */
  103. pci_read_config_dword(pdev, bar, &bar_response);
  104. pci_bus_addr = (pci_addr_t)(bar_response & ~0xf);
  105. /*
  106. * Pass "0" as the length argument to pci_bus_to_virt. The arg
  107. * isn't actualy used on any platform because u-boot assumes a static
  108. * linear mapping. In the future, this could read the BAR size
  109. * and pass that as the size if needed.
  110. */
  111. return pci_bus_to_virt(pdev, pci_bus_addr, flags, 0, MAP_NOCACHE);
  112. }
  113. void pci_write_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum,
  114. u32 addr_and_ctrl)
  115. {
  116. int bar;
  117. bar = PCI_BASE_ADDRESS_0 + barnum * 4;
  118. pci_hose_write_config_dword(hose, dev, bar, addr_and_ctrl);
  119. }
  120. u32 pci_read_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum)
  121. {
  122. u32 addr;
  123. int bar;
  124. bar = PCI_BASE_ADDRESS_0 + barnum * 4;
  125. pci_hose_read_config_dword(hose, dev, bar, &addr);
  126. if (addr & PCI_BASE_ADDRESS_SPACE_IO)
  127. return addr & PCI_BASE_ADDRESS_IO_MASK;
  128. else
  129. return addr & PCI_BASE_ADDRESS_MEM_MASK;
  130. }
  131. int __pci_hose_bus_to_phys(struct pci_controller *hose,
  132. pci_addr_t bus_addr,
  133. unsigned long flags,
  134. unsigned long skip_mask,
  135. phys_addr_t *pa)
  136. {
  137. struct pci_region *res;
  138. int i;
  139. for (i = 0; i < hose->region_count; i++) {
  140. res = &hose->regions[i];
  141. if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
  142. continue;
  143. if (res->flags & skip_mask)
  144. continue;
  145. if (bus_addr >= res->bus_start &&
  146. (bus_addr - res->bus_start) < res->size) {
  147. *pa = (bus_addr - res->bus_start + res->phys_start);
  148. return 0;
  149. }
  150. }
  151. return 1;
  152. }
  153. phys_addr_t pci_hose_bus_to_phys(struct pci_controller *hose,
  154. pci_addr_t bus_addr,
  155. unsigned long flags)
  156. {
  157. phys_addr_t phys_addr = 0;
  158. int ret;
  159. if (!hose) {
  160. puts("pci_hose_bus_to_phys: invalid hose\n");
  161. return phys_addr;
  162. }
  163. /*
  164. * if PCI_REGION_MEM is set we do a two pass search with preference
  165. * on matches that don't have PCI_REGION_SYS_MEMORY set
  166. */
  167. if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
  168. ret = __pci_hose_bus_to_phys(hose, bus_addr,
  169. flags, PCI_REGION_SYS_MEMORY, &phys_addr);
  170. if (!ret)
  171. return phys_addr;
  172. }
  173. ret = __pci_hose_bus_to_phys(hose, bus_addr, flags, 0, &phys_addr);
  174. if (ret)
  175. puts("pci_hose_bus_to_phys: invalid physical address\n");
  176. return phys_addr;
  177. }
  178. int __pci_hose_phys_to_bus(struct pci_controller *hose,
  179. phys_addr_t phys_addr,
  180. unsigned long flags,
  181. unsigned long skip_mask,
  182. pci_addr_t *ba)
  183. {
  184. struct pci_region *res;
  185. pci_addr_t bus_addr;
  186. int i;
  187. for (i = 0; i < hose->region_count; i++) {
  188. res = &hose->regions[i];
  189. if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
  190. continue;
  191. if (res->flags & skip_mask)
  192. continue;
  193. bus_addr = phys_addr - res->phys_start + res->bus_start;
  194. if (bus_addr >= res->bus_start &&
  195. (bus_addr - res->bus_start) < res->size) {
  196. *ba = bus_addr;
  197. return 0;
  198. }
  199. }
  200. return 1;
  201. }
  202. /*
  203. * pci_hose_phys_to_bus(): Convert physical address to bus address
  204. * @hose: PCI hose of the root PCI controller
  205. * @phys_addr: physical address to convert
  206. * @flags: flags of pci regions
  207. * @return bus address if OK, 0 on error
  208. */
  209. pci_addr_t pci_hose_phys_to_bus(struct pci_controller *hose,
  210. phys_addr_t phys_addr,
  211. unsigned long flags)
  212. {
  213. pci_addr_t bus_addr = 0;
  214. int ret;
  215. if (!hose) {
  216. puts("pci_hose_phys_to_bus: invalid hose\n");
  217. return bus_addr;
  218. }
  219. /*
  220. * if PCI_REGION_MEM is set we do a two pass search with preference
  221. * on matches that don't have PCI_REGION_SYS_MEMORY set
  222. */
  223. if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
  224. ret = __pci_hose_phys_to_bus(hose, phys_addr,
  225. flags, PCI_REGION_SYS_MEMORY, &bus_addr);
  226. if (!ret)
  227. return bus_addr;
  228. }
  229. ret = __pci_hose_phys_to_bus(hose, phys_addr, flags, 0, &bus_addr);
  230. if (ret)
  231. puts("pci_hose_phys_to_bus: invalid physical address\n");
  232. return bus_addr;
  233. }
  234. pci_dev_t pci_find_device(unsigned int vendor, unsigned int device, int index)
  235. {
  236. struct pci_device_id ids[2] = { {}, {0, 0} };
  237. ids[0].vendor = vendor;
  238. ids[0].device = device;
  239. return pci_find_devices(ids, index);
  240. }
  241. pci_dev_t pci_hose_find_devices(struct pci_controller *hose, int busnum,
  242. struct pci_device_id *ids, int *indexp)
  243. {
  244. int found_multi = 0;
  245. u16 vendor, device;
  246. u8 header_type;
  247. pci_dev_t bdf;
  248. int i;
  249. for (bdf = PCI_BDF(busnum, 0, 0);
  250. bdf < PCI_BDF(busnum + 1, 0, 0);
  251. bdf += PCI_BDF(0, 0, 1)) {
  252. if (pci_skip_dev(hose, bdf))
  253. continue;
  254. if (!PCI_FUNC(bdf)) {
  255. pci_read_config_byte(bdf, PCI_HEADER_TYPE,
  256. &header_type);
  257. found_multi = header_type & 0x80;
  258. } else {
  259. if (!found_multi)
  260. continue;
  261. }
  262. pci_read_config_word(bdf, PCI_VENDOR_ID, &vendor);
  263. pci_read_config_word(bdf, PCI_DEVICE_ID, &device);
  264. for (i = 0; ids[i].vendor != 0; i++) {
  265. if (vendor == ids[i].vendor &&
  266. device == ids[i].device) {
  267. if ((*indexp) <= 0)
  268. return bdf;
  269. (*indexp)--;
  270. }
  271. }
  272. }
  273. return -1;
  274. }
  275. pci_dev_t pci_find_class(uint find_class, int index)
  276. {
  277. int bus;
  278. int devnum;
  279. pci_dev_t bdf;
  280. uint32_t class;
  281. for (bus = 0; bus <= pci_last_busno(); bus++) {
  282. for (devnum = 0; devnum < PCI_MAX_PCI_DEVICES - 1; devnum++) {
  283. pci_read_config_dword(PCI_BDF(bus, devnum, 0),
  284. PCI_CLASS_REVISION, &class);
  285. if (class >> 16 == 0xffff)
  286. continue;
  287. for (bdf = PCI_BDF(bus, devnum, 0);
  288. bdf <= PCI_BDF(bus, devnum,
  289. PCI_MAX_PCI_FUNCTIONS - 1);
  290. bdf += PCI_BDF(0, 0, 1)) {
  291. pci_read_config_dword(bdf, PCI_CLASS_REVISION,
  292. &class);
  293. class >>= 8;
  294. if (class != find_class)
  295. continue;
  296. /*
  297. * Decrement the index. We want to return the
  298. * correct device, so index is 0 for the first
  299. * matching device, 1 for the second, etc.
  300. */
  301. if (index) {
  302. index--;
  303. continue;
  304. }
  305. /* Return index'th controller. */
  306. return bdf;
  307. }
  308. }
  309. }
  310. return -ENODEV;
  311. }
  312. #endif /* !CONFIG_DM_PCI || CONFIG_DM_PCI_COMPAT */