altera.c 4.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2003
  4. * Steven Scholz, imc Measurement & Control, steven.scholz@imc-berlin.de
  5. *
  6. * (C) Copyright 2002
  7. * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
  8. */
  9. /*
  10. * Altera FPGA support
  11. */
  12. #include <common.h>
  13. #include <errno.h>
  14. #include <ACEX1K.h>
  15. #include <stratixII.h>
  16. /* Define FPGA_DEBUG to 1 to get debug printf's */
  17. #define FPGA_DEBUG 0
  18. static const struct altera_fpga {
  19. enum altera_family family;
  20. const char *name;
  21. int (*load)(Altera_desc *, const void *, size_t);
  22. int (*dump)(Altera_desc *, const void *, size_t);
  23. int (*info)(Altera_desc *);
  24. } altera_fpga[] = {
  25. #if defined(CONFIG_FPGA_ACEX1K)
  26. { Altera_ACEX1K, "ACEX1K", ACEX1K_load, ACEX1K_dump, ACEX1K_info },
  27. { Altera_CYC2, "ACEX1K", ACEX1K_load, ACEX1K_dump, ACEX1K_info },
  28. #elif defined(CONFIG_FPGA_CYCLON2)
  29. { Altera_ACEX1K, "CycloneII", CYC2_load, CYC2_dump, CYC2_info },
  30. { Altera_CYC2, "CycloneII", CYC2_load, CYC2_dump, CYC2_info },
  31. #endif
  32. #if defined(CONFIG_FPGA_STRATIX_II)
  33. { Altera_StratixII, "StratixII", StratixII_load,
  34. StratixII_dump, StratixII_info },
  35. #endif
  36. #if defined(CONFIG_FPGA_STRATIX_V)
  37. { Altera_StratixV, "StratixV", stratixv_load, NULL, NULL },
  38. #endif
  39. #if defined(CONFIG_FPGA_SOCFPGA)
  40. { Altera_SoCFPGA, "SoC FPGA", socfpga_load, NULL, NULL },
  41. #endif
  42. };
  43. static int altera_validate(Altera_desc *desc, const char *fn)
  44. {
  45. if (!desc) {
  46. printf("%s: NULL descriptor!\n", fn);
  47. return -EINVAL;
  48. }
  49. if ((desc->family < min_altera_type) ||
  50. (desc->family > max_altera_type)) {
  51. printf("%s: Invalid family type, %d\n", fn, desc->family);
  52. return -EINVAL;
  53. }
  54. if ((desc->iface < min_altera_iface_type) ||
  55. (desc->iface > max_altera_iface_type)) {
  56. printf("%s: Invalid Interface type, %d\n", fn, desc->iface);
  57. return -EINVAL;
  58. }
  59. if (!desc->size) {
  60. printf("%s: NULL part size\n", fn);
  61. return -EINVAL;
  62. }
  63. return 0;
  64. }
  65. static const struct altera_fpga *
  66. altera_desc_to_fpga(Altera_desc *desc, const char *fn)
  67. {
  68. int i;
  69. if (altera_validate(desc, fn)) {
  70. printf("%s: Invalid device descriptor\n", fn);
  71. return NULL;
  72. }
  73. for (i = 0; i < ARRAY_SIZE(altera_fpga); i++) {
  74. if (desc->family == altera_fpga[i].family)
  75. break;
  76. }
  77. if (i == ARRAY_SIZE(altera_fpga)) {
  78. printf("%s: Unsupported family type, %d\n", fn, desc->family);
  79. return NULL;
  80. }
  81. return &altera_fpga[i];
  82. }
  83. int altera_load(Altera_desc *desc, const void *buf, size_t bsize)
  84. {
  85. const struct altera_fpga *fpga = altera_desc_to_fpga(desc, __func__);
  86. if (!fpga)
  87. return FPGA_FAIL;
  88. debug_cond(FPGA_DEBUG, "%s: Launching the %s Loader...\n",
  89. __func__, fpga->name);
  90. if (fpga->load)
  91. return fpga->load(desc, buf, bsize);
  92. return 0;
  93. }
  94. int altera_dump(Altera_desc *desc, const void *buf, size_t bsize)
  95. {
  96. const struct altera_fpga *fpga = altera_desc_to_fpga(desc, __func__);
  97. if (!fpga)
  98. return FPGA_FAIL;
  99. debug_cond(FPGA_DEBUG, "%s: Launching the %s Reader...\n",
  100. __func__, fpga->name);
  101. if (fpga->dump)
  102. return fpga->dump(desc, buf, bsize);
  103. return 0;
  104. }
  105. int altera_info(Altera_desc *desc)
  106. {
  107. const struct altera_fpga *fpga = altera_desc_to_fpga(desc, __func__);
  108. if (!fpga)
  109. return FPGA_FAIL;
  110. printf("Family: \t%s\n", fpga->name);
  111. printf("Interface type:\t");
  112. switch (desc->iface) {
  113. case passive_serial:
  114. printf("Passive Serial (PS)\n");
  115. break;
  116. case passive_parallel_synchronous:
  117. printf("Passive Parallel Synchronous (PPS)\n");
  118. break;
  119. case passive_parallel_asynchronous:
  120. printf("Passive Parallel Asynchronous (PPA)\n");
  121. break;
  122. case passive_serial_asynchronous:
  123. printf("Passive Serial Asynchronous (PSA)\n");
  124. break;
  125. case altera_jtag_mode: /* Not used */
  126. printf("JTAG Mode\n");
  127. break;
  128. case fast_passive_parallel:
  129. printf("Fast Passive Parallel (FPP)\n");
  130. break;
  131. case fast_passive_parallel_security:
  132. printf("Fast Passive Parallel with Security (FPPS)\n");
  133. break;
  134. /* Add new interface types here */
  135. default:
  136. printf("Unsupported interface type, %d\n", desc->iface);
  137. }
  138. printf("Device Size: \t%zd bytes\n"
  139. "Cookie: \t0x%x (%d)\n",
  140. desc->size, desc->cookie, desc->cookie);
  141. if (desc->iface_fns) {
  142. printf("Device Function Table @ 0x%p\n", desc->iface_fns);
  143. if (fpga->info)
  144. fpga->info(desc);
  145. } else {
  146. printf("No Device Function Table.\n");
  147. }
  148. return FPGA_SUCCESS;
  149. }