mt7628a.dtsi 3.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. / {
  3. #address-cells = <1>;
  4. #size-cells = <1>;
  5. compatible = "ralink,mt7628a-soc";
  6. cpus {
  7. #address-cells = <1>;
  8. #size-cells = <0>;
  9. cpu@0 {
  10. compatible = "mti,mips24KEc";
  11. device_type = "cpu";
  12. reg = <0>;
  13. };
  14. };
  15. resetc: reset-controller {
  16. compatible = "ralink,rt2880-reset";
  17. #reset-cells = <1>;
  18. };
  19. cpuintc: interrupt-controller {
  20. #address-cells = <0>;
  21. #interrupt-cells = <1>;
  22. interrupt-controller;
  23. compatible = "mti,cpu-interrupt-controller";
  24. };
  25. palmbus@10000000 {
  26. compatible = "palmbus", "simple-bus";
  27. reg = <0x10000000 0x200000>;
  28. ranges = <0x0 0x10000000 0x1FFFFF>;
  29. #address-cells = <1>;
  30. #size-cells = <1>;
  31. sysc: system-controller@0 {
  32. compatible = "ralink,mt7620a-sysc", "syscon";
  33. reg = <0x0 0x100>;
  34. };
  35. syscon-reboot {
  36. compatible = "syscon-reboot";
  37. regmap = <&sysc>;
  38. offset = <0x34>;
  39. mask = <0x1>;
  40. };
  41. watchdog: watchdog@100 {
  42. compatible = "ralink,mt7628a-wdt", "mediatek,mt7621-wdt";
  43. reg = <0x100 0x30>;
  44. resets = <&resetc 8>;
  45. reset-names = "wdt";
  46. interrupt-parent = <&intc>;
  47. interrupts = <24>;
  48. };
  49. intc: interrupt-controller@200 {
  50. compatible = "ralink,rt2880-intc";
  51. reg = <0x200 0x100>;
  52. interrupt-controller;
  53. #interrupt-cells = <1>;
  54. resets = <&resetc 9>;
  55. reset-names = "intc";
  56. interrupt-parent = <&cpuintc>;
  57. interrupts = <2>;
  58. ralink,intc-registers = <0x9c 0xa0
  59. 0x6c 0xa4
  60. 0x80 0x78>;
  61. };
  62. memory-controller@300 {
  63. compatible = "ralink,mt7620a-memc";
  64. reg = <0x300 0x100>;
  65. };
  66. gpio@600 {
  67. #address-cells = <1>;
  68. #size-cells = <0>;
  69. compatible = "mtk,mt7628-gpio", "mtk,mt7621-gpio";
  70. reg = <0x600 0x100>;
  71. interrupt-parent = <&intc>;
  72. interrupts = <6>;
  73. gpio0: bank@0 {
  74. reg = <0>;
  75. compatible = "mtk,mt7621-gpio-bank";
  76. gpio-controller;
  77. #gpio-cells = <2>;
  78. };
  79. gpio1: bank@1 {
  80. reg = <1>;
  81. compatible = "mtk,mt7621-gpio-bank";
  82. gpio-controller;
  83. #gpio-cells = <2>;
  84. };
  85. gpio2: bank@2 {
  86. reg = <2>;
  87. compatible = "mtk,mt7621-gpio-bank";
  88. gpio-controller;
  89. #gpio-cells = <2>;
  90. };
  91. };
  92. spi0: spi@b00 {
  93. compatible = "ralink,mt7621-spi";
  94. reg = <0xb00 0x40>;
  95. #address-cells = <1>;
  96. #size-cells = <0>;
  97. clock-frequency = <200000000>;
  98. };
  99. uart0: uartlite@c00 {
  100. compatible = "ns16550a";
  101. reg = <0xc00 0x100>;
  102. resets = <&resetc 12>;
  103. reset-names = "uart0";
  104. interrupt-parent = <&intc>;
  105. interrupts = <20>;
  106. reg-shift = <2>;
  107. };
  108. uart1: uart1@d00 {
  109. compatible = "ns16550a";
  110. reg = <0xd00 0x100>;
  111. resets = <&resetc 19>;
  112. reset-names = "uart1";
  113. interrupt-parent = <&intc>;
  114. interrupts = <21>;
  115. reg-shift = <2>;
  116. };
  117. uart2: uart2@e00 {
  118. compatible = "ns16550a";
  119. reg = <0xe00 0x100>;
  120. resets = <&resetc 20>;
  121. reset-names = "uart2";
  122. interrupt-parent = <&intc>;
  123. interrupts = <22>;
  124. reg-shift = <2>;
  125. };
  126. };
  127. eth@10110000 {
  128. compatible = "mediatek,mt7622-eth";
  129. reg = <0x10100000 0x10000
  130. 0x10110000 0x8000>;
  131. syscon = <&sysc>;
  132. };
  133. usb_phy: usb-phy@10120000 {
  134. compatible = "mediatek,mt7628-usbphy";
  135. reg = <0x10120000 0x1000>;
  136. #phy-cells = <0>;
  137. ralink,sysctl = <&sysc>;
  138. resets = <&resetc 22 &resetc 25>;
  139. reset-names = "host", "device";
  140. };
  141. ehci@101c0000 {
  142. compatible = "generic-ehci";
  143. reg = <0x101c0000 0x1000>;
  144. phys = <&usb_phy>;
  145. phy-names = "usb";
  146. interrupt-parent = <&intc>;
  147. interrupts = <18>;
  148. };
  149. };