devices.c 2.1 KB

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  1. /*
  2. * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #include <common.h>
  7. #include <asm/arch/cpu.h>
  8. #include <asm/arch/clk.h>
  9. #include <asm/arch/uart.h>
  10. #include <asm/arch/mux.h>
  11. #include <asm/io.h>
  12. #include <dm.h>
  13. static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
  14. static struct uart_ctrl_regs *ctrl = (struct uart_ctrl_regs *)UART_CTRL_BASE;
  15. static struct mux_regs *mux = (struct mux_regs *)MUX_BASE;
  16. void lpc32xx_uart_init(unsigned int uart_id)
  17. {
  18. if (uart_id < 1 || uart_id > 7)
  19. return;
  20. /* Disable loopback mode, if it is set by S1L bootloader */
  21. clrbits_le32(&ctrl->loop,
  22. UART_LOOPBACK(CONFIG_SYS_LPC32XX_UART));
  23. if (uart_id < 3 || uart_id > 6)
  24. return;
  25. /* Enable UART system clock */
  26. setbits_le32(&clk->uartclk_ctrl, CLK_UART(uart_id));
  27. /* Set UART into autoclock mode */
  28. clrsetbits_le32(&ctrl->clkmode,
  29. UART_CLKMODE_MASK(uart_id),
  30. UART_CLKMODE_AUTO(uart_id));
  31. /* Bypass pre-divider of UART clock */
  32. writel(CLK_UART_X_DIV(1) | CLK_UART_Y_DIV(1),
  33. &clk->u3clk + (uart_id - 3));
  34. }
  35. void lpc32xx_mac_init(void)
  36. {
  37. /* Enable MAC interface */
  38. writel(CLK_MAC_REG | CLK_MAC_SLAVE | CLK_MAC_MASTER
  39. #if defined(CONFIG_RMII)
  40. | CLK_MAC_RMII,
  41. #else
  42. | CLK_MAC_MII,
  43. #endif
  44. &clk->macclk_ctrl);
  45. }
  46. void lpc32xx_mlc_nand_init(void)
  47. {
  48. /* Enable NAND interface */
  49. writel(CLK_NAND_MLC | CLK_NAND_MLC_INT, &clk->flashclk_ctrl);
  50. }
  51. void lpc32xx_slc_nand_init(void)
  52. {
  53. /* Enable SLC NAND interface */
  54. writel(CLK_NAND_SLC | CLK_NAND_SLC_SELECT, &clk->flashclk_ctrl);
  55. }
  56. void lpc32xx_i2c_init(unsigned int devnum)
  57. {
  58. /* Enable I2C interface */
  59. uint32_t ctrl = readl(&clk->i2cclk_ctrl);
  60. if (devnum == 1)
  61. ctrl |= CLK_I2C1_ENABLE;
  62. if (devnum == 2)
  63. ctrl |= CLK_I2C2_ENABLE;
  64. writel(ctrl, &clk->i2cclk_ctrl);
  65. }
  66. U_BOOT_DEVICE(lpc32xx_gpios) = {
  67. .name = "gpio_lpc32xx"
  68. };
  69. /* Mux for SCK0, MISO0, MOSI0. We do not use SSEL0. */
  70. #define P_MUX_SET_SSP0 0x1600
  71. void lpc32xx_ssp_init(void)
  72. {
  73. /* Enable SSP0 interface */
  74. writel(CLK_SSP0_ENABLE_CLOCK, &clk->ssp_ctrl);
  75. /* Mux SSP0 pins */
  76. writel(P_MUX_SET_SSP0, &mux->p_mux_set);
  77. }