spi_flash.c 13 KB

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  1. /*
  2. * SPI flash interface
  3. *
  4. * Copyright (C) 2008 Atmel Corporation
  5. * Copyright (C) 2010 Reinhard Meyer, EMK Elektronik
  6. *
  7. * Licensed under the GPL-2 or later.
  8. */
  9. #include <common.h>
  10. #include <fdtdec.h>
  11. #include <malloc.h>
  12. #include <spi.h>
  13. #include <spi_flash.h>
  14. #include <watchdog.h>
  15. #include "spi_flash_internal.h"
  16. DECLARE_GLOBAL_DATA_PTR;
  17. static void spi_flash_addr(u32 addr, u8 *cmd)
  18. {
  19. /* cmd[0] is actual command */
  20. cmd[1] = addr >> 16;
  21. cmd[2] = addr >> 8;
  22. cmd[3] = addr >> 0;
  23. }
  24. static int spi_flash_read_write(struct spi_slave *spi,
  25. const u8 *cmd, size_t cmd_len,
  26. const u8 *data_out, u8 *data_in,
  27. size_t data_len)
  28. {
  29. unsigned long flags = SPI_XFER_BEGIN;
  30. int ret;
  31. if (data_len == 0)
  32. flags |= SPI_XFER_END;
  33. ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags);
  34. if (ret) {
  35. debug("SF: Failed to send command (%zu bytes): %d\n",
  36. cmd_len, ret);
  37. } else if (data_len != 0) {
  38. ret = spi_xfer(spi, data_len * 8, data_out, data_in, SPI_XFER_END);
  39. if (ret)
  40. debug("SF: Failed to transfer %zu bytes of data: %d\n",
  41. data_len, ret);
  42. }
  43. return ret;
  44. }
  45. int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len)
  46. {
  47. return spi_flash_cmd_read(spi, &cmd, 1, response, len);
  48. }
  49. int spi_flash_cmd_read(struct spi_slave *spi, const u8 *cmd,
  50. size_t cmd_len, void *data, size_t data_len)
  51. {
  52. return spi_flash_read_write(spi, cmd, cmd_len, NULL, data, data_len);
  53. }
  54. int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len,
  55. const void *data, size_t data_len)
  56. {
  57. return spi_flash_read_write(spi, cmd, cmd_len, data, NULL, data_len);
  58. }
  59. int spi_flash_cmd_write_multi(struct spi_flash *flash, u32 offset,
  60. size_t len, const void *buf)
  61. {
  62. unsigned long page_addr, byte_addr, page_size;
  63. size_t chunk_len, actual;
  64. int ret;
  65. u8 cmd[4], bank_sel;
  66. page_size = flash->page_size;
  67. ret = spi_claim_bus(flash->spi);
  68. if (ret) {
  69. debug("SF: unable to claim SPI bus\n");
  70. return ret;
  71. }
  72. cmd[0] = CMD_PAGE_PROGRAM;
  73. for (actual = 0; actual < len; actual += chunk_len) {
  74. bank_sel = offset / SPI_FLASH_16MB_BOUN;
  75. ret = spi_flash_cmd_bankaddr_write(flash, bank_sel);
  76. if (ret) {
  77. debug("SF: fail to set bank%d\n", bank_sel);
  78. return ret;
  79. }
  80. page_addr = offset / page_size;
  81. byte_addr = offset % page_size;
  82. chunk_len = min(len - actual, page_size - byte_addr);
  83. if (flash->spi->max_write_size)
  84. chunk_len = min(chunk_len, flash->spi->max_write_size);
  85. cmd[1] = page_addr >> 8;
  86. cmd[2] = page_addr;
  87. cmd[3] = byte_addr;
  88. debug("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n",
  89. buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
  90. ret = spi_flash_cmd_write_enable(flash);
  91. if (ret < 0) {
  92. debug("SF: enabling write failed\n");
  93. break;
  94. }
  95. ret = spi_flash_cmd_write(flash->spi, cmd, 4,
  96. buf + actual, chunk_len);
  97. if (ret < 0) {
  98. debug("SF: write failed\n");
  99. break;
  100. }
  101. ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
  102. if (ret)
  103. break;
  104. offset += chunk_len;
  105. }
  106. spi_release_bus(flash->spi);
  107. return ret;
  108. }
  109. int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd,
  110. size_t cmd_len, void *data, size_t data_len)
  111. {
  112. struct spi_slave *spi = flash->spi;
  113. int ret;
  114. spi_claim_bus(spi);
  115. ret = spi_flash_cmd_read(spi, cmd, cmd_len, data, data_len);
  116. spi_release_bus(spi);
  117. return ret;
  118. }
  119. int spi_flash_cmd_read_fast(struct spi_flash *flash, u32 offset,
  120. size_t len, void *data)
  121. {
  122. u8 cmd[5], bank_sel;
  123. u32 remain_len, read_len;
  124. int ret = -1;
  125. /* Handle memory-mapped SPI */
  126. if (flash->memory_map) {
  127. memcpy(data, flash->memory_map + offset, len);
  128. return 0;
  129. }
  130. cmd[0] = CMD_READ_ARRAY_FAST;
  131. cmd[4] = 0x00;
  132. while (len) {
  133. bank_sel = offset / SPI_FLASH_16MB_BOUN;
  134. ret = spi_flash_cmd_bankaddr_write(flash, bank_sel);
  135. if (ret) {
  136. debug("SF: fail to set bank%d\n", bank_sel);
  137. return ret;
  138. }
  139. remain_len = (SPI_FLASH_16MB_BOUN * (bank_sel + 1) - offset);
  140. if (len < remain_len)
  141. read_len = len;
  142. else
  143. read_len = remain_len;
  144. spi_flash_addr(offset, cmd);
  145. ret = spi_flash_read_common(flash, cmd, sizeof(cmd),
  146. data, read_len);
  147. if (ret < 0) {
  148. debug("SF: read failed\n");
  149. break;
  150. }
  151. offset += read_len;
  152. len -= read_len;
  153. data += read_len;
  154. }
  155. return ret;
  156. }
  157. int spi_flash_cmd_poll_bit(struct spi_flash *flash, unsigned long timeout,
  158. u8 cmd, u8 poll_bit)
  159. {
  160. struct spi_slave *spi = flash->spi;
  161. unsigned long timebase;
  162. int ret;
  163. u8 status;
  164. ret = spi_xfer(spi, 8, &cmd, NULL, SPI_XFER_BEGIN);
  165. if (ret) {
  166. debug("SF: Failed to send command %02x: %d\n", cmd, ret);
  167. return ret;
  168. }
  169. timebase = get_timer(0);
  170. do {
  171. WATCHDOG_RESET();
  172. ret = spi_xfer(spi, 8, NULL, &status, 0);
  173. if (ret)
  174. return -1;
  175. if ((status & poll_bit) == 0)
  176. break;
  177. } while (get_timer(timebase) < timeout);
  178. spi_xfer(spi, 0, NULL, NULL, SPI_XFER_END);
  179. if ((status & poll_bit) == 0)
  180. return 0;
  181. /* Timed out */
  182. debug("SF: time out!\n");
  183. return -1;
  184. }
  185. int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout)
  186. {
  187. return spi_flash_cmd_poll_bit(flash, timeout,
  188. CMD_READ_STATUS, STATUS_WIP);
  189. }
  190. int spi_flash_cmd_erase(struct spi_flash *flash, u32 offset, size_t len)
  191. {
  192. u32 erase_size;
  193. int ret;
  194. u8 cmd[4], bank_sel;
  195. erase_size = flash->sector_size;
  196. if (offset % erase_size || len % erase_size) {
  197. debug("SF: Erase offset/length not multiple of erase size\n");
  198. return -1;
  199. }
  200. ret = spi_claim_bus(flash->spi);
  201. if (ret) {
  202. debug("SF: Unable to claim SPI bus\n");
  203. return ret;
  204. }
  205. if (erase_size == 4096)
  206. cmd[0] = CMD_ERASE_4K;
  207. else
  208. cmd[0] = CMD_ERASE_64K;
  209. while (len) {
  210. bank_sel = offset / SPI_FLASH_16MB_BOUN;
  211. ret = spi_flash_cmd_bankaddr_write(flash, bank_sel);
  212. if (ret) {
  213. debug("SF: fail to set bank%d\n", bank_sel);
  214. return ret;
  215. }
  216. spi_flash_addr(offset, cmd);
  217. debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1],
  218. cmd[2], cmd[3], offset);
  219. ret = spi_flash_cmd_write_enable(flash);
  220. if (ret)
  221. goto out;
  222. ret = spi_flash_cmd_write(flash->spi, cmd, sizeof(cmd), NULL, 0);
  223. if (ret)
  224. goto out;
  225. ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PAGE_ERASE_TIMEOUT);
  226. if (ret)
  227. goto out;
  228. offset += erase_size;
  229. len -= erase_size;
  230. }
  231. out:
  232. spi_release_bus(flash->spi);
  233. return ret;
  234. }
  235. int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr)
  236. {
  237. u8 cmd;
  238. int ret;
  239. ret = spi_flash_cmd_write_enable(flash);
  240. if (ret < 0) {
  241. debug("SF: enabling write failed\n");
  242. return ret;
  243. }
  244. cmd = CMD_WRITE_STATUS;
  245. ret = spi_flash_cmd_write(flash->spi, &cmd, 1, &sr, 1);
  246. if (ret) {
  247. debug("SF: fail to write status register\n");
  248. return ret;
  249. }
  250. ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
  251. if (ret < 0) {
  252. debug("SF: write status register timed out\n");
  253. return ret;
  254. }
  255. return 0;
  256. }
  257. int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 bank_sel)
  258. {
  259. u8 cmd;
  260. int ret;
  261. if (flash->bank_curr == bank_sel) {
  262. debug("SF: not require to enable bank%d\n", bank_sel);
  263. return 0;
  264. }
  265. cmd = flash->bank_write_cmd;
  266. ret = spi_flash_cmd_write_enable(flash);
  267. if (ret < 0) {
  268. debug("SF: enabling write failed\n");
  269. return ret;
  270. }
  271. ret = spi_flash_cmd_write(flash->spi, &cmd, 1, &bank_sel, 1);
  272. if (ret) {
  273. debug("SF: fail to write bank addr register\n");
  274. return ret;
  275. }
  276. flash->bank_curr = bank_sel;
  277. ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
  278. if (ret < 0) {
  279. debug("SF: write bank addr register timed out\n");
  280. return ret;
  281. }
  282. return 0;
  283. }
  284. int spi_flash_bank_config(struct spi_flash *flash, u8 idcode0)
  285. {
  286. u8 cmd;
  287. u8 curr_bank = 0;
  288. /* discover bank cmds */
  289. switch (idcode0) {
  290. case SPI_FLASH_SPANSION_IDCODE0:
  291. flash->bank_read_cmd = CMD_BANKADDR_BRRD;
  292. flash->bank_write_cmd = CMD_BANKADDR_BRWR;
  293. break;
  294. case SPI_FLASH_STMICRO_IDCODE0:
  295. case SPI_FLASH_WINBOND_IDCODE0:
  296. flash->bank_read_cmd = CMD_EXTNADDR_RDEAR;
  297. flash->bank_write_cmd = CMD_EXTNADDR_WREAR;
  298. break;
  299. default:
  300. printf("SF: Unsupported bank commands %02x\n", idcode0);
  301. return -1;
  302. }
  303. /* read the bank reg - on which bank the flash is in currently */
  304. cmd = flash->bank_read_cmd;
  305. if (flash->size > SPI_FLASH_16MB_BOUN) {
  306. if (spi_flash_read_common(flash, &cmd, 1, &curr_bank, 1)) {
  307. debug("SF: fail to read bank addr register\n");
  308. return -1;
  309. }
  310. flash->bank_curr = curr_bank;
  311. } else {
  312. flash->bank_curr = curr_bank;
  313. }
  314. return 0;
  315. }
  316. #ifdef CONFIG_OF_CONTROL
  317. int spi_flash_decode_fdt(const void *blob, struct spi_flash *flash)
  318. {
  319. fdt_addr_t addr;
  320. fdt_size_t size;
  321. int node;
  322. /* If there is no node, do nothing */
  323. node = fdtdec_next_compatible(blob, 0, COMPAT_GENERIC_SPI_FLASH);
  324. if (node < 0)
  325. return 0;
  326. addr = fdtdec_get_addr_size(blob, node, "memory-map", &size);
  327. if (addr == FDT_ADDR_T_NONE) {
  328. debug("%s: Cannot decode address\n", __func__);
  329. return 0;
  330. }
  331. if (flash->size != size) {
  332. debug("%s: Memory map must cover entire device\n", __func__);
  333. return -1;
  334. }
  335. flash->memory_map = (void *)addr;
  336. return 0;
  337. }
  338. #endif /* CONFIG_OF_CONTROL */
  339. /*
  340. * The following table holds all device probe functions
  341. *
  342. * shift: number of continuation bytes before the ID
  343. * idcode: the expected IDCODE or 0xff for non JEDEC devices
  344. * probe: the function to call
  345. *
  346. * Non JEDEC devices should be ordered in the table such that
  347. * the probe functions with best detection algorithms come first.
  348. *
  349. * Several matching entries are permitted, they will be tried
  350. * in sequence until a probe function returns non NULL.
  351. *
  352. * IDCODE_CONT_LEN may be redefined if a device needs to declare a
  353. * larger "shift" value. IDCODE_PART_LEN generally shouldn't be
  354. * changed. This is the max number of bytes probe functions may
  355. * examine when looking up part-specific identification info.
  356. *
  357. * Probe functions will be given the idcode buffer starting at their
  358. * manu id byte (the "idcode" in the table below). In other words,
  359. * all of the continuation bytes will be skipped (the "shift" below).
  360. */
  361. #define IDCODE_CONT_LEN 0
  362. #define IDCODE_PART_LEN 5
  363. static const struct {
  364. const u8 shift;
  365. const u8 idcode;
  366. struct spi_flash *(*probe) (struct spi_slave *spi, u8 *idcode);
  367. } flashes[] = {
  368. /* Keep it sorted by define name */
  369. #ifdef CONFIG_SPI_FLASH_ATMEL
  370. { 0, 0x1f, spi_flash_probe_atmel, },
  371. #endif
  372. #ifdef CONFIG_SPI_FLASH_EON
  373. { 0, 0x1c, spi_flash_probe_eon, },
  374. #endif
  375. #ifdef CONFIG_SPI_FLASH_MACRONIX
  376. { 0, 0xc2, spi_flash_probe_macronix, },
  377. #endif
  378. #ifdef CONFIG_SPI_FLASH_SPANSION
  379. { 0, 0x01, spi_flash_probe_spansion, },
  380. #endif
  381. #ifdef CONFIG_SPI_FLASH_SST
  382. { 0, 0xbf, spi_flash_probe_sst, },
  383. #endif
  384. #ifdef CONFIG_SPI_FLASH_STMICRO
  385. { 0, 0x20, spi_flash_probe_stmicro, },
  386. #endif
  387. #ifdef CONFIG_SPI_FLASH_WINBOND
  388. { 0, 0xef, spi_flash_probe_winbond, },
  389. #endif
  390. #ifdef CONFIG_SPI_FRAM_RAMTRON
  391. { 6, 0xc2, spi_fram_probe_ramtron, },
  392. # undef IDCODE_CONT_LEN
  393. # define IDCODE_CONT_LEN 6
  394. #endif
  395. /* Keep it sorted by best detection */
  396. #ifdef CONFIG_SPI_FLASH_STMICRO
  397. { 0, 0xff, spi_flash_probe_stmicro, },
  398. #endif
  399. #ifdef CONFIG_SPI_FRAM_RAMTRON_NON_JEDEC
  400. { 0, 0xff, spi_fram_probe_ramtron, },
  401. #endif
  402. };
  403. #define IDCODE_LEN (IDCODE_CONT_LEN + IDCODE_PART_LEN)
  404. struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
  405. unsigned int max_hz, unsigned int spi_mode)
  406. {
  407. struct spi_slave *spi;
  408. struct spi_flash *flash = NULL;
  409. int ret, i, shift;
  410. u8 idcode[IDCODE_LEN], *idp;
  411. spi = spi_setup_slave(bus, cs, max_hz, spi_mode);
  412. if (!spi) {
  413. printf("SF: Failed to set up slave\n");
  414. return NULL;
  415. }
  416. ret = spi_claim_bus(spi);
  417. if (ret) {
  418. debug("SF: Failed to claim SPI bus: %d\n", ret);
  419. goto err_claim_bus;
  420. }
  421. /* Read the ID codes */
  422. ret = spi_flash_cmd(spi, CMD_READ_ID, idcode, sizeof(idcode));
  423. if (ret)
  424. goto err_read_id;
  425. #ifdef DEBUG
  426. printf("SF: Got idcodes\n");
  427. print_buffer(0, idcode, 1, sizeof(idcode), 0);
  428. #endif
  429. /* count the number of continuation bytes */
  430. for (shift = 0, idp = idcode;
  431. shift < IDCODE_CONT_LEN && *idp == 0x7f;
  432. ++shift, ++idp)
  433. continue;
  434. /* search the table for matches in shift and id */
  435. for (i = 0; i < ARRAY_SIZE(flashes); ++i)
  436. if (flashes[i].shift == shift && flashes[i].idcode == *idp) {
  437. /* we have a match, call probe */
  438. flash = flashes[i].probe(spi, idp);
  439. if (flash)
  440. break;
  441. }
  442. if (!flash) {
  443. printf("SF: Unsupported manufacturer %02x\n", *idp);
  444. goto err_manufacturer_probe;
  445. }
  446. /* Configure the BAR - disover bank cmds and read current bank */
  447. ret = spi_flash_bank_config(flash, *idp);
  448. if (ret < 0)
  449. goto err_manufacturer_probe;
  450. #ifdef CONFIG_OF_CONTROL
  451. if (spi_flash_decode_fdt(gd->fdt_blob, flash)) {
  452. debug("SF: FDT decode error\n");
  453. goto err_manufacturer_probe;
  454. }
  455. #endif
  456. printf("SF: Detected %s with page size ", flash->name);
  457. print_size(flash->sector_size, ", total ");
  458. print_size(flash->size, "");
  459. if (flash->memory_map)
  460. printf(", mapped at %p", flash->memory_map);
  461. puts("\n");
  462. spi_release_bus(spi);
  463. return flash;
  464. err_manufacturer_probe:
  465. err_read_id:
  466. spi_release_bus(spi);
  467. err_claim_bus:
  468. spi_free_slave(spi);
  469. return NULL;
  470. }
  471. void *spi_flash_do_alloc(int offset, int size, struct spi_slave *spi,
  472. const char *name)
  473. {
  474. struct spi_flash *flash;
  475. void *ptr;
  476. ptr = malloc(size);
  477. if (!ptr) {
  478. debug("SF: Failed to allocate memory\n");
  479. return NULL;
  480. }
  481. memset(ptr, '\0', size);
  482. flash = (struct spi_flash *)(ptr + offset);
  483. /* Set up some basic fields - caller will sort out sizes */
  484. flash->spi = spi;
  485. flash->name = name;
  486. flash->read = spi_flash_cmd_read_fast;
  487. flash->write = spi_flash_cmd_write_multi;
  488. flash->erase = spi_flash_cmd_erase;
  489. return flash;
  490. }
  491. void spi_flash_free(struct spi_flash *flash)
  492. {
  493. spi_free_slave(flash->spi);
  494. free(flash);
  495. }