cpu.c 3.2 KB

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  1. /*
  2. * (C) Copyright 2003
  3. * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. #include <common.h>
  8. #include <command.h>
  9. #include <netdev.h>
  10. #include <asm/mipsregs.h>
  11. #include <asm/cacheops.h>
  12. #include <asm/reboot.h>
  13. #define cache_op(op,addr) \
  14. __asm__ __volatile__( \
  15. " .set push \n" \
  16. " .set noreorder \n" \
  17. " .set mips3\n\t \n" \
  18. " cache %0, %1 \n" \
  19. " .set pop \n" \
  20. : \
  21. : "i" (op), "R" (*(unsigned char *)(addr)))
  22. void __attribute__((weak)) _machine_restart(void)
  23. {
  24. }
  25. int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
  26. {
  27. _machine_restart();
  28. fprintf(stderr, "*** reset failed ***\n");
  29. return 0;
  30. }
  31. #ifdef CONFIG_SYS_CACHELINE_SIZE
  32. static inline unsigned long icache_line_size(void)
  33. {
  34. return CONFIG_SYS_CACHELINE_SIZE;
  35. }
  36. static inline unsigned long dcache_line_size(void)
  37. {
  38. return CONFIG_SYS_CACHELINE_SIZE;
  39. }
  40. #else /* !CONFIG_SYS_CACHELINE_SIZE */
  41. static inline unsigned long icache_line_size(void)
  42. {
  43. unsigned long conf1, il;
  44. conf1 = read_c0_config1();
  45. il = (conf1 & MIPS_CONF1_IL) >> MIPS_CONF1_IL_SHIFT;
  46. if (!il)
  47. return 0;
  48. return 2 << il;
  49. }
  50. static inline unsigned long dcache_line_size(void)
  51. {
  52. unsigned long conf1, dl;
  53. conf1 = read_c0_config1();
  54. dl = (conf1 & MIPS_CONF1_DL) >> MIPS_CONF1_DL_SHIFT;
  55. if (!dl)
  56. return 0;
  57. return 2 << dl;
  58. }
  59. #endif /* !CONFIG_SYS_CACHELINE_SIZE */
  60. void flush_cache(ulong start_addr, ulong size)
  61. {
  62. unsigned long ilsize = icache_line_size();
  63. unsigned long dlsize = dcache_line_size();
  64. unsigned long addr, aend;
  65. /* aend will be miscalculated when size is zero, so we return here */
  66. if (size == 0)
  67. return;
  68. addr = start_addr & ~(dlsize - 1);
  69. aend = (start_addr + size - 1) & ~(dlsize - 1);
  70. if (ilsize == dlsize) {
  71. /* flush I-cache & D-cache simultaneously */
  72. while (1) {
  73. cache_op(HIT_WRITEBACK_INV_D, addr);
  74. cache_op(HIT_INVALIDATE_I, addr);
  75. if (addr == aend)
  76. break;
  77. addr += dlsize;
  78. }
  79. return;
  80. }
  81. /* flush D-cache */
  82. while (1) {
  83. cache_op(HIT_WRITEBACK_INV_D, addr);
  84. if (addr == aend)
  85. break;
  86. addr += dlsize;
  87. }
  88. /* flush I-cache */
  89. addr = start_addr & ~(ilsize - 1);
  90. aend = (start_addr + size - 1) & ~(ilsize - 1);
  91. while (1) {
  92. cache_op(HIT_INVALIDATE_I, addr);
  93. if (addr == aend)
  94. break;
  95. addr += ilsize;
  96. }
  97. }
  98. void flush_dcache_range(ulong start_addr, ulong stop)
  99. {
  100. unsigned long lsize = dcache_line_size();
  101. unsigned long addr = start_addr & ~(lsize - 1);
  102. unsigned long aend = (stop - 1) & ~(lsize - 1);
  103. while (1) {
  104. cache_op(HIT_WRITEBACK_INV_D, addr);
  105. if (addr == aend)
  106. break;
  107. addr += lsize;
  108. }
  109. }
  110. void invalidate_dcache_range(ulong start_addr, ulong stop)
  111. {
  112. unsigned long lsize = dcache_line_size();
  113. unsigned long addr = start_addr & ~(lsize - 1);
  114. unsigned long aend = (stop - 1) & ~(lsize - 1);
  115. while (1) {
  116. cache_op(HIT_INVALIDATE_D, addr);
  117. if (addr == aend)
  118. break;
  119. addr += lsize;
  120. }
  121. }
  122. void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1)
  123. {
  124. write_c0_entrylo0(low0);
  125. write_c0_pagemask(pagemask);
  126. write_c0_entrylo1(low1);
  127. write_c0_entryhi(hi);
  128. write_c0_index(index);
  129. tlb_write_indexed();
  130. }
  131. int cpu_eth_init(bd_t *bis)
  132. {
  133. #ifdef CONFIG_SOC_AU1X00
  134. au1x00_enet_initialize(bis);
  135. #endif
  136. return 0;
  137. }