serial_sh.c 6.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325
  1. /*
  2. * SuperH SCIF device driver.
  3. * Copyright (C) 2013 Renesas Electronics Corporation
  4. * Copyright (C) 2007,2008,2010, 2014 Nobuhiro Iwamatsu
  5. * Copyright (C) 2002 - 2008 Paul Mundt
  6. *
  7. * SPDX-License-Identifier: GPL-2.0+
  8. */
  9. #include <common.h>
  10. #include <errno.h>
  11. #include <dm.h>
  12. #include <asm/io.h>
  13. #include <asm/processor.h>
  14. #include <serial.h>
  15. #include <linux/compiler.h>
  16. #include <dm/platform_data/serial_sh.h>
  17. #include "serial_sh.h"
  18. #if defined(CONFIG_CPU_SH7760) || \
  19. defined(CONFIG_CPU_SH7780) || \
  20. defined(CONFIG_CPU_SH7785) || \
  21. defined(CONFIG_CPU_SH7786)
  22. static int scif_rxfill(struct uart_port *port)
  23. {
  24. return sci_in(port, SCRFDR) & 0xff;
  25. }
  26. #elif defined(CONFIG_CPU_SH7763)
  27. static int scif_rxfill(struct uart_port *port)
  28. {
  29. if ((port->mapbase == 0xffe00000) ||
  30. (port->mapbase == 0xffe08000)) {
  31. /* SCIF0/1*/
  32. return sci_in(port, SCRFDR) & 0xff;
  33. } else {
  34. /* SCIF2 */
  35. return sci_in(port, SCFDR) & SCIF2_RFDC_MASK;
  36. }
  37. }
  38. #elif defined(CONFIG_ARCH_SH7372)
  39. static int scif_rxfill(struct uart_port *port)
  40. {
  41. if (port->type == PORT_SCIFA)
  42. return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
  43. else
  44. return sci_in(port, SCRFDR);
  45. }
  46. #else
  47. static int scif_rxfill(struct uart_port *port)
  48. {
  49. return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
  50. }
  51. #endif
  52. static void sh_serial_init_generic(struct uart_port *port)
  53. {
  54. sci_out(port, SCSCR , SCSCR_INIT(port));
  55. sci_out(port, SCSCR , SCSCR_INIT(port));
  56. sci_out(port, SCSMR, 0);
  57. sci_out(port, SCSMR, 0);
  58. sci_out(port, SCFCR, SCFCR_RFRST|SCFCR_TFRST);
  59. sci_in(port, SCFCR);
  60. sci_out(port, SCFCR, 0);
  61. }
  62. static void
  63. sh_serial_setbrg_generic(struct uart_port *port, int clk, int baudrate)
  64. {
  65. if (port->clk_mode == EXT_CLK) {
  66. unsigned short dl = DL_VALUE(baudrate, clk);
  67. sci_out(port, DL, dl);
  68. /* Need wait: Clock * 1/dl * 1/16 */
  69. udelay((1000000 * dl * 16 / clk) * 1000 + 1);
  70. } else {
  71. sci_out(port, SCBRR, SCBRR_VALUE(baudrate, clk));
  72. }
  73. }
  74. static void handle_error(struct uart_port *port)
  75. {
  76. sci_in(port, SCxSR);
  77. sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
  78. sci_in(port, SCLSR);
  79. sci_out(port, SCLSR, 0x00);
  80. }
  81. static int serial_raw_putc(struct uart_port *port, const char c)
  82. {
  83. /* Tx fifo is empty */
  84. if (!(sci_in(port, SCxSR) & SCxSR_TEND(port)))
  85. return -EAGAIN;
  86. sci_out(port, SCxTDR, c);
  87. sci_out(port, SCxSR, sci_in(port, SCxSR) & ~SCxSR_TEND(port));
  88. return 0;
  89. }
  90. static int serial_rx_fifo_level(struct uart_port *port)
  91. {
  92. return scif_rxfill(port);
  93. }
  94. static int sh_serial_tstc_generic(struct uart_port *port)
  95. {
  96. if (sci_in(port, SCxSR) & SCIF_ERRORS) {
  97. handle_error(port);
  98. return 0;
  99. }
  100. return serial_rx_fifo_level(port) ? 1 : 0;
  101. }
  102. static int serial_getc_check(struct uart_port *port)
  103. {
  104. unsigned short status;
  105. status = sci_in(port, SCxSR);
  106. if (status & SCIF_ERRORS)
  107. handle_error(port);
  108. if (sci_in(port, SCLSR) & SCxSR_ORER(port))
  109. handle_error(port);
  110. return status & (SCIF_DR | SCxSR_RDxF(port));
  111. }
  112. static int sh_serial_getc_generic(struct uart_port *port)
  113. {
  114. unsigned short status;
  115. char ch;
  116. if (!serial_getc_check(port))
  117. return -EAGAIN;
  118. ch = sci_in(port, SCxRDR);
  119. status = sci_in(port, SCxSR);
  120. sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
  121. if (status & SCIF_ERRORS)
  122. handle_error(port);
  123. if (sci_in(port, SCLSR) & SCxSR_ORER(port))
  124. handle_error(port);
  125. return ch;
  126. }
  127. #ifdef CONFIG_DM_SERIAL
  128. static int sh_serial_pending(struct udevice *dev, bool input)
  129. {
  130. struct uart_port *priv = dev_get_priv(dev);
  131. return sh_serial_tstc_generic(priv);
  132. }
  133. static int sh_serial_putc(struct udevice *dev, const char ch)
  134. {
  135. struct uart_port *priv = dev_get_priv(dev);
  136. return serial_raw_putc(priv, ch);
  137. }
  138. static int sh_serial_getc(struct udevice *dev)
  139. {
  140. struct uart_port *priv = dev_get_priv(dev);
  141. return sh_serial_getc_generic(priv);
  142. }
  143. static int sh_serial_setbrg(struct udevice *dev, int baudrate)
  144. {
  145. struct sh_serial_platdata *plat = dev_get_platdata(dev);
  146. struct uart_port *priv = dev_get_priv(dev);
  147. sh_serial_setbrg_generic(priv, plat->clk, baudrate);
  148. return 0;
  149. }
  150. static int sh_serial_probe(struct udevice *dev)
  151. {
  152. struct sh_serial_platdata *plat = dev_get_platdata(dev);
  153. struct uart_port *priv = dev_get_priv(dev);
  154. priv->membase = (unsigned char *)plat->base;
  155. priv->mapbase = plat->base;
  156. priv->type = plat->type;
  157. priv->clk_mode = plat->clk_mode;
  158. sh_serial_init_generic(priv);
  159. return 0;
  160. }
  161. static const struct dm_serial_ops sh_serial_ops = {
  162. .putc = sh_serial_putc,
  163. .pending = sh_serial_pending,
  164. .getc = sh_serial_getc,
  165. .setbrg = sh_serial_setbrg,
  166. };
  167. U_BOOT_DRIVER(serial_sh) = {
  168. .name = "serial_sh",
  169. .id = UCLASS_SERIAL,
  170. .probe = sh_serial_probe,
  171. .ops = &sh_serial_ops,
  172. .flags = DM_FLAG_PRE_RELOC,
  173. .priv_auto_alloc_size = sizeof(struct uart_port),
  174. };
  175. #else /* CONFIG_DM_SERIAL */
  176. #if defined(CONFIG_CONS_SCIF0)
  177. # define SCIF_BASE SCIF0_BASE
  178. #elif defined(CONFIG_CONS_SCIF1)
  179. # define SCIF_BASE SCIF1_BASE
  180. #elif defined(CONFIG_CONS_SCIF2)
  181. # define SCIF_BASE SCIF2_BASE
  182. #elif defined(CONFIG_CONS_SCIF3)
  183. # define SCIF_BASE SCIF3_BASE
  184. #elif defined(CONFIG_CONS_SCIF4)
  185. # define SCIF_BASE SCIF4_BASE
  186. #elif defined(CONFIG_CONS_SCIF5)
  187. # define SCIF_BASE SCIF5_BASE
  188. #elif defined(CONFIG_CONS_SCIF6)
  189. # define SCIF_BASE SCIF6_BASE
  190. #elif defined(CONFIG_CONS_SCIF7)
  191. # define SCIF_BASE SCIF7_BASE
  192. #else
  193. # error "Default SCIF doesn't set....."
  194. #endif
  195. #if defined(CONFIG_SCIF_A)
  196. #define SCIF_BASE_PORT PORT_SCIFA
  197. #else
  198. #define SCIF_BASE_PORT PORT_SCIF
  199. #endif
  200. static struct uart_port sh_sci = {
  201. .membase = (unsigned char *)SCIF_BASE,
  202. .mapbase = SCIF_BASE,
  203. .type = SCIF_BASE_PORT,
  204. #ifdef CONFIG_SCIF_USE_EXT_CLK
  205. .clk_mode = EXT_CLK,
  206. #endif
  207. };
  208. static void sh_serial_setbrg(void)
  209. {
  210. DECLARE_GLOBAL_DATA_PTR;
  211. struct uart_port *port = &sh_sci;
  212. sh_serial_setbrg_generic(port, CONFIG_SH_SCIF_CLK_FREQ, gd->baudrate);
  213. }
  214. static int sh_serial_init(void)
  215. {
  216. struct uart_port *port = &sh_sci;
  217. sh_serial_init_generic(port);
  218. serial_setbrg();
  219. return 0;
  220. }
  221. static void sh_serial_putc(const char c)
  222. {
  223. struct uart_port *port = &sh_sci;
  224. if (c == '\n') {
  225. while (1) {
  226. if (serial_raw_putc(port, '\r') != -EAGAIN)
  227. break;
  228. }
  229. }
  230. while (1) {
  231. if (serial_raw_putc(port, c) != -EAGAIN)
  232. break;
  233. }
  234. }
  235. static int sh_serial_tstc(void)
  236. {
  237. struct uart_port *port = &sh_sci;
  238. return sh_serial_tstc_generic(port);
  239. }
  240. static int sh_serial_getc(void)
  241. {
  242. struct uart_port *port = &sh_sci;
  243. int ch;
  244. while (1) {
  245. ch = sh_serial_getc_generic(port);
  246. if (ch != -EAGAIN)
  247. break;
  248. }
  249. return ch;
  250. }
  251. static struct serial_device sh_serial_drv = {
  252. .name = "sh_serial",
  253. .start = sh_serial_init,
  254. .stop = NULL,
  255. .setbrg = sh_serial_setbrg,
  256. .putc = sh_serial_putc,
  257. .puts = default_serial_puts,
  258. .getc = sh_serial_getc,
  259. .tstc = sh_serial_tstc,
  260. };
  261. void sh_serial_initialize(void)
  262. {
  263. serial_register(&sh_serial_drv);
  264. }
  265. __weak struct serial_device *default_serial_console(void)
  266. {
  267. return &sh_serial_drv;
  268. }
  269. #endif /* CONFIG_DM_SERIAL */