fsl_i2c.c 15 KB

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  1. /*
  2. * Copyright 2006,2009 Freescale Semiconductor, Inc.
  3. *
  4. * 2012, Heiko Schocher, DENX Software Engineering, hs@denx.de.
  5. * Changes for multibus/multiadapter I2C support.
  6. *
  7. * SPDX-License-Identifier: GPL-2.0
  8. */
  9. #include <common.h>
  10. #include <command.h>
  11. #include <i2c.h> /* Functional interface */
  12. #include <asm/io.h>
  13. #include <asm/fsl_i2c.h> /* HW definitions */
  14. /* The maximum number of microseconds we will wait until another master has
  15. * released the bus. If not defined in the board header file, then use a
  16. * generic value.
  17. */
  18. #ifndef CONFIG_I2C_MBB_TIMEOUT
  19. #define CONFIG_I2C_MBB_TIMEOUT 100000
  20. #endif
  21. /* The maximum number of microseconds we will wait for a read or write
  22. * operation to complete. If not defined in the board header file, then use a
  23. * generic value.
  24. */
  25. #ifndef CONFIG_I2C_TIMEOUT
  26. #define CONFIG_I2C_TIMEOUT 100000
  27. #endif
  28. #define I2C_READ_BIT 1
  29. #define I2C_WRITE_BIT 0
  30. DECLARE_GLOBAL_DATA_PTR;
  31. static const struct fsl_i2c *i2c_dev[4] = {
  32. (struct fsl_i2c *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C_OFFSET),
  33. #ifdef CONFIG_SYS_FSL_I2C2_OFFSET
  34. (struct fsl_i2c *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C2_OFFSET),
  35. #endif
  36. #ifdef CONFIG_SYS_FSL_I2C3_OFFSET
  37. (struct fsl_i2c *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C3_OFFSET),
  38. #endif
  39. #ifdef CONFIG_SYS_FSL_I2C4_OFFSET
  40. (struct fsl_i2c *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C4_OFFSET)
  41. #endif
  42. };
  43. /* I2C speed map for a DFSR value of 1 */
  44. /*
  45. * Map I2C frequency dividers to FDR and DFSR values
  46. *
  47. * This structure is used to define the elements of a table that maps I2C
  48. * frequency divider (I2C clock rate divided by I2C bus speed) to a value to be
  49. * programmed into the Frequency Divider Ratio (FDR) and Digital Filter
  50. * Sampling Rate (DFSR) registers.
  51. *
  52. * The actual table should be defined in the board file, and it must be called
  53. * fsl_i2c_speed_map[].
  54. *
  55. * The last entry of the table must have a value of {-1, X}, where X is same
  56. * FDR/DFSR values as the second-to-last entry. This guarantees that any
  57. * search through the array will always find a match.
  58. *
  59. * The values of the divider must be in increasing numerical order, i.e.
  60. * fsl_i2c_speed_map[x+1].divider > fsl_i2c_speed_map[x].divider.
  61. *
  62. * For this table, the values are based on a value of 1 for the DFSR
  63. * register. See the application note AN2919 "Determining the I2C Frequency
  64. * Divider Ratio for SCL"
  65. *
  66. * ColdFire I2C frequency dividers for FDR values are different from
  67. * PowerPC. The protocol to use the I2C module is still the same.
  68. * A different table is defined and are based on MCF5xxx user manual.
  69. *
  70. */
  71. static const struct {
  72. unsigned short divider;
  73. u8 fdr;
  74. } fsl_i2c_speed_map[] = {
  75. #ifdef __M68K__
  76. {20, 32}, {22, 33}, {24, 34}, {26, 35},
  77. {28, 0}, {28, 36}, {30, 1}, {32, 37},
  78. {34, 2}, {36, 38}, {40, 3}, {40, 39},
  79. {44, 4}, {48, 5}, {48, 40}, {56, 6},
  80. {56, 41}, {64, 42}, {68, 7}, {72, 43},
  81. {80, 8}, {80, 44}, {88, 9}, {96, 41},
  82. {104, 10}, {112, 42}, {128, 11}, {128, 43},
  83. {144, 12}, {160, 13}, {160, 48}, {192, 14},
  84. {192, 49}, {224, 50}, {240, 15}, {256, 51},
  85. {288, 16}, {320, 17}, {320, 52}, {384, 18},
  86. {384, 53}, {448, 54}, {480, 19}, {512, 55},
  87. {576, 20}, {640, 21}, {640, 56}, {768, 22},
  88. {768, 57}, {960, 23}, {896, 58}, {1024, 59},
  89. {1152, 24}, {1280, 25}, {1280, 60}, {1536, 26},
  90. {1536, 61}, {1792, 62}, {1920, 27}, {2048, 63},
  91. {2304, 28}, {2560, 29}, {3072, 30}, {3840, 31},
  92. {-1, 31}
  93. #endif
  94. };
  95. /**
  96. * Set the I2C bus speed for a given I2C device
  97. *
  98. * @param dev: the I2C device
  99. * @i2c_clk: I2C bus clock frequency
  100. * @speed: the desired speed of the bus
  101. *
  102. * The I2C device must be stopped before calling this function.
  103. *
  104. * The return value is the actual bus speed that is set.
  105. */
  106. static unsigned int set_i2c_bus_speed(const struct fsl_i2c *dev,
  107. unsigned int i2c_clk, unsigned int speed)
  108. {
  109. unsigned short divider = min(i2c_clk / speed, (unsigned int)USHRT_MAX);
  110. /*
  111. * We want to choose an FDR/DFSR that generates an I2C bus speed that
  112. * is equal to or lower than the requested speed. That means that we
  113. * want the first divider that is equal to or greater than the
  114. * calculated divider.
  115. */
  116. #ifdef __PPC__
  117. u8 dfsr, fdr = 0x31; /* Default if no FDR found */
  118. /* a, b and dfsr matches identifiers A,B and C respectively in AN2919 */
  119. unsigned short a, b, ga, gb;
  120. unsigned long c_div, est_div;
  121. #ifdef CONFIG_FSL_I2C_CUSTOM_DFSR
  122. dfsr = CONFIG_FSL_I2C_CUSTOM_DFSR;
  123. #else
  124. /* Condition 1: dfsr <= 50/T */
  125. dfsr = (5 * (i2c_clk / 1000)) / 100000;
  126. #endif
  127. #ifdef CONFIG_FSL_I2C_CUSTOM_FDR
  128. fdr = CONFIG_FSL_I2C_CUSTOM_FDR;
  129. speed = i2c_clk / divider; /* Fake something */
  130. #else
  131. debug("Requested speed:%d, i2c_clk:%d\n", speed, i2c_clk);
  132. if (!dfsr)
  133. dfsr = 1;
  134. est_div = ~0;
  135. for (ga = 0x4, a = 10; a <= 30; ga++, a += 2) {
  136. for (gb = 0; gb < 8; gb++) {
  137. b = 16 << gb;
  138. c_div = b * (a + ((3*dfsr)/b)*2);
  139. if ((c_div > divider) && (c_div < est_div)) {
  140. unsigned short bin_gb, bin_ga;
  141. est_div = c_div;
  142. bin_gb = gb << 2;
  143. bin_ga = (ga & 0x3) | ((ga & 0x4) << 3);
  144. fdr = bin_gb | bin_ga;
  145. speed = i2c_clk / est_div;
  146. debug("FDR:0x%.2x, div:%ld, ga:0x%x, gb:0x%x, "
  147. "a:%d, b:%d, speed:%d\n",
  148. fdr, est_div, ga, gb, a, b, speed);
  149. /* Condition 2 not accounted for */
  150. debug("Tr <= %d ns\n",
  151. (b - 3 * dfsr) * 1000000 /
  152. (i2c_clk / 1000));
  153. }
  154. }
  155. if (a == 20)
  156. a += 2;
  157. if (a == 24)
  158. a += 4;
  159. }
  160. debug("divider:%d, est_div:%ld, DFSR:%d\n", divider, est_div, dfsr);
  161. debug("FDR:0x%.2x, speed:%d\n", fdr, speed);
  162. #endif
  163. writeb(dfsr, &dev->dfsrr); /* set default filter */
  164. writeb(fdr, &dev->fdr); /* set bus speed */
  165. #else
  166. unsigned int i;
  167. for (i = 0; i < ARRAY_SIZE(fsl_i2c_speed_map); i++)
  168. if (fsl_i2c_speed_map[i].divider >= divider) {
  169. u8 fdr;
  170. fdr = fsl_i2c_speed_map[i].fdr;
  171. speed = i2c_clk / fsl_i2c_speed_map[i].divider;
  172. writeb(fdr, &dev->fdr); /* set bus speed */
  173. break;
  174. }
  175. #endif
  176. return speed;
  177. }
  178. static unsigned int get_i2c_clock(int bus)
  179. {
  180. if (bus)
  181. return gd->arch.i2c2_clk; /* I2C2 clock */
  182. else
  183. return gd->arch.i2c1_clk; /* I2C1 clock */
  184. }
  185. static int fsl_i2c_fixup(const struct fsl_i2c *dev)
  186. {
  187. const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
  188. unsigned long long timeval = 0;
  189. int ret = -1;
  190. unsigned int flags = 0;
  191. #ifdef CONFIG_SYS_FSL_ERRATUM_I2C_A004447
  192. unsigned int svr = get_svr();
  193. if ((SVR_SOC_VER(svr) == SVR_8548 && IS_SVR_REV(svr, 3, 1)) ||
  194. (SVR_REV(svr) <= CONFIG_SYS_FSL_A004447_SVR_REV))
  195. flags = I2C_CR_BIT6;
  196. #endif
  197. writeb(I2C_CR_MEN | I2C_CR_MSTA, &dev->cr);
  198. timeval = get_ticks();
  199. while (!(readb(&dev->sr) & I2C_SR_MBB)) {
  200. if ((get_ticks() - timeval) > timeout)
  201. goto err;
  202. }
  203. if (readb(&dev->sr) & I2C_SR_MAL) {
  204. /* SDA is stuck low */
  205. writeb(0, &dev->cr);
  206. udelay(100);
  207. writeb(I2C_CR_MSTA | flags, &dev->cr);
  208. writeb(I2C_CR_MEN | I2C_CR_MSTA | flags, &dev->cr);
  209. }
  210. readb(&dev->dr);
  211. timeval = get_ticks();
  212. while (!(readb(&dev->sr) & I2C_SR_MIF)) {
  213. if ((get_ticks() - timeval) > timeout)
  214. goto err;
  215. }
  216. ret = 0;
  217. err:
  218. writeb(I2C_CR_MEN | flags, &dev->cr);
  219. writeb(0, &dev->sr);
  220. udelay(100);
  221. return ret;
  222. }
  223. static void fsl_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
  224. {
  225. const struct fsl_i2c *dev;
  226. const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
  227. unsigned long long timeval;
  228. #ifdef CONFIG_SYS_I2C_INIT_BOARD
  229. /* Call board specific i2c bus reset routine before accessing the
  230. * environment, which might be in a chip on that bus. For details
  231. * about this problem see doc/I2C_Edge_Conditions.
  232. */
  233. i2c_init_board();
  234. #endif
  235. dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
  236. writeb(0, &dev->cr); /* stop I2C controller */
  237. udelay(5); /* let it shutdown in peace */
  238. set_i2c_bus_speed(dev, get_i2c_clock(adap->hwadapnr), speed);
  239. writeb(slaveadd << 1, &dev->adr);/* write slave address */
  240. writeb(0x0, &dev->sr); /* clear status register */
  241. writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */
  242. timeval = get_ticks();
  243. while (readb(&dev->sr) & I2C_SR_MBB) {
  244. if ((get_ticks() - timeval) < timeout)
  245. continue;
  246. if (fsl_i2c_fixup(dev))
  247. debug("i2c_init: BUS#%d failed to init\n",
  248. adap->hwadapnr);
  249. break;
  250. }
  251. #ifdef CONFIG_SYS_I2C_BOARD_LATE_INIT
  252. /* Call board specific i2c bus reset routine AFTER the bus has been
  253. * initialized. Use either this callpoint or i2c_init_board;
  254. * which is called before i2c_init operations.
  255. * For details about this problem see doc/I2C_Edge_Conditions.
  256. */
  257. i2c_board_late_init();
  258. #endif
  259. }
  260. static int
  261. i2c_wait4bus(struct i2c_adapter *adap)
  262. {
  263. struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
  264. unsigned long long timeval = get_ticks();
  265. const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
  266. while (readb(&dev->sr) & I2C_SR_MBB) {
  267. if ((get_ticks() - timeval) > timeout)
  268. return -1;
  269. }
  270. return 0;
  271. }
  272. static __inline__ int
  273. i2c_wait(struct i2c_adapter *adap, int write)
  274. {
  275. u32 csr;
  276. unsigned long long timeval = get_ticks();
  277. const unsigned long long timeout = usec2ticks(CONFIG_I2C_TIMEOUT);
  278. struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
  279. do {
  280. csr = readb(&dev->sr);
  281. if (!(csr & I2C_SR_MIF))
  282. continue;
  283. /* Read again to allow register to stabilise */
  284. csr = readb(&dev->sr);
  285. writeb(0x0, &dev->sr);
  286. if (csr & I2C_SR_MAL) {
  287. debug("i2c_wait: MAL\n");
  288. return -1;
  289. }
  290. if (!(csr & I2C_SR_MCF)) {
  291. debug("i2c_wait: unfinished\n");
  292. return -1;
  293. }
  294. if (write == I2C_WRITE_BIT && (csr & I2C_SR_RXAK)) {
  295. debug("i2c_wait: No RXACK\n");
  296. return -1;
  297. }
  298. return 0;
  299. } while ((get_ticks() - timeval) < timeout);
  300. debug("i2c_wait: timed out\n");
  301. return -1;
  302. }
  303. static __inline__ int
  304. i2c_write_addr(struct i2c_adapter *adap, u8 dev, u8 dir, int rsta)
  305. {
  306. struct fsl_i2c *device = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
  307. writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX
  308. | (rsta ? I2C_CR_RSTA : 0),
  309. &device->cr);
  310. writeb((dev << 1) | dir, &device->dr);
  311. if (i2c_wait(adap, I2C_WRITE_BIT) < 0)
  312. return 0;
  313. return 1;
  314. }
  315. static __inline__ int
  316. __i2c_write(struct i2c_adapter *adap, u8 *data, int length)
  317. {
  318. struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
  319. int i;
  320. for (i = 0; i < length; i++) {
  321. writeb(data[i], &dev->dr);
  322. if (i2c_wait(adap, I2C_WRITE_BIT) < 0)
  323. break;
  324. }
  325. return i;
  326. }
  327. static __inline__ int
  328. __i2c_read(struct i2c_adapter *adap, u8 *data, int length)
  329. {
  330. struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
  331. int i;
  332. writeb(I2C_CR_MEN | I2C_CR_MSTA | ((length == 1) ? I2C_CR_TXAK : 0),
  333. &dev->cr);
  334. /* dummy read */
  335. readb(&dev->dr);
  336. for (i = 0; i < length; i++) {
  337. if (i2c_wait(adap, I2C_READ_BIT) < 0)
  338. break;
  339. /* Generate ack on last next to last byte */
  340. if (i == length - 2)
  341. writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_TXAK,
  342. &dev->cr);
  343. /* Do not generate stop on last byte */
  344. if (i == length - 1)
  345. writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX,
  346. &dev->cr);
  347. data[i] = readb(&dev->dr);
  348. }
  349. return i;
  350. }
  351. static int
  352. fsl_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr, int alen, u8 *data,
  353. int length)
  354. {
  355. struct fsl_i2c *device = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
  356. int i = -1; /* signal error */
  357. u8 *a = (u8*)&addr;
  358. int len = alen * -1;
  359. if (i2c_wait4bus(adap) < 0)
  360. return -1;
  361. /* To handle the need of I2C devices that require to write few bytes
  362. * (more than 4 bytes of address as in the case of else part)
  363. * of data before reading, Negative equivalent of length(bytes to write)
  364. * is passed, but used the +ve part of len for writing data
  365. */
  366. if (alen < 0) {
  367. /* Generate a START and send the Address and
  368. * the Tx Bytes to the slave.
  369. * "START: Address: Write bytes data[len]"
  370. * IF part supports writing any number of bytes in contrast
  371. * to the else part, which supports writing address offset
  372. * of upto 4 bytes only.
  373. * bytes that need to be written are passed in
  374. * "data", which will eventually keep the data READ,
  375. * after writing the len bytes out of it
  376. */
  377. if (i2c_write_addr(adap, dev, I2C_WRITE_BIT, 0) != 0)
  378. i = __i2c_write(adap, data, len);
  379. if (i != len)
  380. return -1;
  381. if (length && i2c_write_addr(adap, dev, I2C_READ_BIT, 1) != 0)
  382. i = __i2c_read(adap, data, length);
  383. } else {
  384. if ((!length || alen > 0) &&
  385. i2c_write_addr(adap, dev, I2C_WRITE_BIT, 0) != 0 &&
  386. __i2c_write(adap, &a[4 - alen], alen) == alen)
  387. i = 0; /* No error so far */
  388. if (length &&
  389. i2c_write_addr(adap, dev, I2C_READ_BIT, alen ? 1 : 0) != 0)
  390. i = __i2c_read(adap, data, length);
  391. }
  392. writeb(I2C_CR_MEN, &device->cr);
  393. if (i2c_wait4bus(adap)) /* Wait until STOP */
  394. debug("i2c_read: wait4bus timed out\n");
  395. if (i == length)
  396. return 0;
  397. return -1;
  398. }
  399. static int
  400. fsl_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr, int alen,
  401. u8 *data, int length)
  402. {
  403. struct fsl_i2c *device = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
  404. int i = -1; /* signal error */
  405. u8 *a = (u8*)&addr;
  406. if (i2c_wait4bus(adap) < 0)
  407. return -1;
  408. if (i2c_write_addr(adap, dev, I2C_WRITE_BIT, 0) != 0 &&
  409. __i2c_write(adap, &a[4 - alen], alen) == alen) {
  410. i = __i2c_write(adap, data, length);
  411. }
  412. writeb(I2C_CR_MEN, &device->cr);
  413. if (i2c_wait4bus(adap)) /* Wait until STOP */
  414. debug("i2c_write: wait4bus timed out\n");
  415. if (i == length)
  416. return 0;
  417. return -1;
  418. }
  419. static int
  420. fsl_i2c_probe(struct i2c_adapter *adap, uchar chip)
  421. {
  422. struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
  423. /* For unknow reason the controller will ACK when
  424. * probing for a slave with the same address, so skip
  425. * it.
  426. */
  427. if (chip == (readb(&dev->adr) >> 1))
  428. return -1;
  429. return fsl_i2c_read(adap, chip, 0, 0, NULL, 0);
  430. }
  431. static unsigned int fsl_i2c_set_bus_speed(struct i2c_adapter *adap,
  432. unsigned int speed)
  433. {
  434. struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
  435. writeb(0, &dev->cr); /* stop controller */
  436. set_i2c_bus_speed(dev, get_i2c_clock(adap->hwadapnr), speed);
  437. writeb(I2C_CR_MEN, &dev->cr); /* start controller */
  438. return 0;
  439. }
  440. /*
  441. * Register fsl i2c adapters
  442. */
  443. U_BOOT_I2C_ADAP_COMPLETE(fsl_0, fsl_i2c_init, fsl_i2c_probe, fsl_i2c_read,
  444. fsl_i2c_write, fsl_i2c_set_bus_speed,
  445. CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE,
  446. 0)
  447. #ifdef CONFIG_SYS_FSL_I2C2_OFFSET
  448. U_BOOT_I2C_ADAP_COMPLETE(fsl_1, fsl_i2c_init, fsl_i2c_probe, fsl_i2c_read,
  449. fsl_i2c_write, fsl_i2c_set_bus_speed,
  450. CONFIG_SYS_FSL_I2C2_SPEED, CONFIG_SYS_FSL_I2C2_SLAVE,
  451. 1)
  452. #endif
  453. #ifdef CONFIG_SYS_FSL_I2C3_OFFSET
  454. U_BOOT_I2C_ADAP_COMPLETE(fsl_2, fsl_i2c_init, fsl_i2c_probe, fsl_i2c_read,
  455. fsl_i2c_write, fsl_i2c_set_bus_speed,
  456. CONFIG_SYS_FSL_I2C3_SPEED, CONFIG_SYS_FSL_I2C3_SLAVE,
  457. 2)
  458. #endif
  459. #ifdef CONFIG_SYS_FSL_I2C4_OFFSET
  460. U_BOOT_I2C_ADAP_COMPLETE(fsl_3, fsl_i2c_init, fsl_i2c_probe, fsl_i2c_read,
  461. fsl_i2c_write, fsl_i2c_set_bus_speed,
  462. CONFIG_SYS_FSL_I2C4_SPEED, CONFIG_SYS_FSL_I2C4_SLAVE,
  463. 3)
  464. #endif