adi_i2c.c 7.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305
  1. /*
  2. * i2c.c - driver for ADI TWI/I2C
  3. *
  4. * Copyright (c) 2006-2014 Analog Devices Inc.
  5. *
  6. * Licensed under the GPL-2 or later.
  7. */
  8. #include <common.h>
  9. #include <i2c.h>
  10. #include <asm/clock.h>
  11. #include <asm/twi.h>
  12. #include <asm/io.h>
  13. static struct twi_regs *i2c_get_base(struct i2c_adapter *adap);
  14. /* Every register is 32bit aligned, but only 16bits in size */
  15. #define ureg(name) u16 name; u16 __pad_##name;
  16. struct twi_regs {
  17. ureg(clkdiv);
  18. ureg(control);
  19. ureg(slave_ctl);
  20. ureg(slave_stat);
  21. ureg(slave_addr);
  22. ureg(master_ctl);
  23. ureg(master_stat);
  24. ureg(master_addr);
  25. ureg(int_stat);
  26. ureg(int_mask);
  27. ureg(fifo_ctl);
  28. ureg(fifo_stat);
  29. char __pad[0x50];
  30. ureg(xmt_data8);
  31. ureg(xmt_data16);
  32. ureg(rcv_data8);
  33. ureg(rcv_data16);
  34. };
  35. #undef ureg
  36. #ifdef TWI_CLKDIV
  37. #define TWI0_CLKDIV TWI_CLKDIV
  38. # ifdef CONFIG_SYS_MAX_I2C_BUS
  39. # undef CONFIG_SYS_MAX_I2C_BUS
  40. # endif
  41. #define CONFIG_SYS_MAX_I2C_BUS 1
  42. #endif
  43. /*
  44. * The way speed is changed into duty often results in integer truncation
  45. * with 50% duty, so we'll force rounding up to the next duty by adding 1
  46. * to the max. In practice this will get us a speed of something like
  47. * 385 KHz. The other limit is easy to handle as it is only 8 bits.
  48. */
  49. #define I2C_SPEED_MAX 400000
  50. #define I2C_SPEED_TO_DUTY(speed) (5000000 / (speed))
  51. #define I2C_DUTY_MAX (I2C_SPEED_TO_DUTY(I2C_SPEED_MAX) + 1)
  52. #define I2C_DUTY_MIN 0xff /* 8 bit limited */
  53. #define SYS_I2C_DUTY I2C_SPEED_TO_DUTY(CONFIG_SYS_I2C_SPEED)
  54. /* Note: duty is inverse of speed, so the comparisons below are correct */
  55. #if SYS_I2C_DUTY < I2C_DUTY_MAX || SYS_I2C_DUTY > I2C_DUTY_MIN
  56. # error "The I2C hardware can only operate 20KHz - 400KHz"
  57. #endif
  58. /* All transfers are described by this data structure */
  59. struct adi_i2c_msg {
  60. u8 flags;
  61. #define I2C_M_COMBO 0x4
  62. #define I2C_M_STOP 0x2
  63. #define I2C_M_READ 0x1
  64. int len; /* msg length */
  65. u8 *buf; /* pointer to msg data */
  66. int alen; /* addr length */
  67. u8 *abuf; /* addr buffer */
  68. };
  69. /* Allow msec timeout per ~byte transfer */
  70. #define I2C_TIMEOUT 10
  71. /**
  72. * wait_for_completion - manage the actual i2c transfer
  73. * @msg: the i2c msg
  74. */
  75. static int wait_for_completion(struct twi_regs *twi, struct adi_i2c_msg *msg)
  76. {
  77. u16 int_stat, ctl;
  78. ulong timebase = get_timer(0);
  79. do {
  80. int_stat = readw(&twi->int_stat);
  81. if (int_stat & XMTSERV) {
  82. writew(XMTSERV, &twi->int_stat);
  83. if (msg->alen) {
  84. writew(*(msg->abuf++), &twi->xmt_data8);
  85. --msg->alen;
  86. } else if (!(msg->flags & I2C_M_COMBO) && msg->len) {
  87. writew(*(msg->buf++), &twi->xmt_data8);
  88. --msg->len;
  89. } else {
  90. ctl = readw(&twi->master_ctl);
  91. if (msg->flags & I2C_M_COMBO)
  92. writew(ctl | RSTART | MDIR,
  93. &twi->master_ctl);
  94. else
  95. writew(ctl | STOP, &twi->master_ctl);
  96. }
  97. }
  98. if (int_stat & RCVSERV) {
  99. writew(RCVSERV, &twi->int_stat);
  100. if (msg->len) {
  101. *(msg->buf++) = readw(&twi->rcv_data8);
  102. --msg->len;
  103. } else if (msg->flags & I2C_M_STOP) {
  104. ctl = readw(&twi->master_ctl);
  105. writew(ctl | STOP, &twi->master_ctl);
  106. }
  107. }
  108. if (int_stat & MERR) {
  109. writew(MERR, &twi->int_stat);
  110. return msg->len;
  111. }
  112. if (int_stat & MCOMP) {
  113. writew(MCOMP, &twi->int_stat);
  114. if (msg->flags & I2C_M_COMBO && msg->len) {
  115. ctl = readw(&twi->master_ctl);
  116. ctl = (ctl & ~RSTART) |
  117. (min(msg->len, 0xff) << 6) | MEN | MDIR;
  118. writew(ctl, &twi->master_ctl);
  119. } else
  120. break;
  121. }
  122. /* If we were able to do something, reset timeout */
  123. if (int_stat)
  124. timebase = get_timer(0);
  125. } while (get_timer(timebase) < I2C_TIMEOUT);
  126. return msg->len;
  127. }
  128. static int i2c_transfer(struct i2c_adapter *adap, uint8_t chip, uint addr,
  129. int alen, uint8_t *buffer, int len, uint8_t flags)
  130. {
  131. struct twi_regs *twi = i2c_get_base(adap);
  132. int ret;
  133. u16 ctl;
  134. uchar addr_buffer[] = {
  135. (addr >> 0),
  136. (addr >> 8),
  137. (addr >> 16),
  138. };
  139. struct adi_i2c_msg msg = {
  140. .flags = flags | (len >= 0xff ? I2C_M_STOP : 0),
  141. .buf = buffer,
  142. .len = len,
  143. .abuf = addr_buffer,
  144. .alen = alen,
  145. };
  146. /* wait for things to settle */
  147. while (readw(&twi->master_stat) & BUSBUSY)
  148. if (ctrlc())
  149. return 1;
  150. /* Set Transmit device address */
  151. writew(chip, &twi->master_addr);
  152. /* Clear the FIFO before starting things */
  153. writew(XMTFLUSH | RCVFLUSH, &twi->fifo_ctl);
  154. writew(0, &twi->fifo_ctl);
  155. /* prime the pump */
  156. if (msg.alen) {
  157. len = (msg.flags & I2C_M_COMBO) ? msg.alen : msg.alen + len;
  158. writew(*(msg.abuf++), &twi->xmt_data8);
  159. --msg.alen;
  160. } else if (!(msg.flags & I2C_M_READ) && msg.len) {
  161. writew(*(msg.buf++), &twi->xmt_data8);
  162. --msg.len;
  163. }
  164. /* clear int stat */
  165. writew(-1, &twi->master_stat);
  166. writew(-1, &twi->int_stat);
  167. writew(0, &twi->int_mask);
  168. /* Master enable */
  169. ctl = readw(&twi->master_ctl);
  170. ctl = (ctl & FAST) | (min(len, 0xff) << 6) | MEN |
  171. ((msg.flags & I2C_M_READ) ? MDIR : 0);
  172. writew(ctl, &twi->master_ctl);
  173. /* process the rest */
  174. ret = wait_for_completion(twi, &msg);
  175. if (ret) {
  176. ctl = readw(&twi->master_ctl) & ~MEN;
  177. writew(ctl, &twi->master_ctl);
  178. ctl = readw(&twi->control) & ~TWI_ENA;
  179. writew(ctl, &twi->control);
  180. ctl = readw(&twi->control) | TWI_ENA;
  181. writew(ctl, &twi->control);
  182. }
  183. return ret;
  184. }
  185. static uint adi_i2c_setspeed(struct i2c_adapter *adap, uint speed)
  186. {
  187. struct twi_regs *twi = i2c_get_base(adap);
  188. u16 clkdiv = I2C_SPEED_TO_DUTY(speed);
  189. /* Set TWI interface clock */
  190. if (clkdiv < I2C_DUTY_MAX || clkdiv > I2C_DUTY_MIN)
  191. return -1;
  192. clkdiv = (clkdiv << 8) | (clkdiv & 0xff);
  193. writew(clkdiv, &twi->clkdiv);
  194. /* Don't turn it on */
  195. writew(speed > 100000 ? FAST : 0, &twi->master_ctl);
  196. return 0;
  197. }
  198. static void adi_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
  199. {
  200. struct twi_regs *twi = i2c_get_base(adap);
  201. u16 prescale = ((get_i2c_clk() / 1000 / 1000 + 5) / 10) & 0x7F;
  202. /* Set TWI internal clock as 10MHz */
  203. writew(prescale, &twi->control);
  204. /* Set TWI interface clock as specified */
  205. i2c_set_bus_speed(speed);
  206. /* Enable it */
  207. writew(TWI_ENA | prescale, &twi->control);
  208. }
  209. static int adi_i2c_read(struct i2c_adapter *adap, uint8_t chip,
  210. uint addr, int alen, uint8_t *buffer, int len)
  211. {
  212. return i2c_transfer(adap, chip, addr, alen, buffer,
  213. len, alen ? I2C_M_COMBO : I2C_M_READ);
  214. }
  215. static int adi_i2c_write(struct i2c_adapter *adap, uint8_t chip,
  216. uint addr, int alen, uint8_t *buffer, int len)
  217. {
  218. return i2c_transfer(adap, chip, addr, alen, buffer, len, 0);
  219. }
  220. static int adi_i2c_probe(struct i2c_adapter *adap, uint8_t chip)
  221. {
  222. u8 byte;
  223. return adi_i2c_read(adap, chip, 0, 0, &byte, 1);
  224. }
  225. static struct twi_regs *i2c_get_base(struct i2c_adapter *adap)
  226. {
  227. switch (adap->hwadapnr) {
  228. #if CONFIG_SYS_MAX_I2C_BUS > 2
  229. case 2:
  230. return (struct twi_regs *)TWI2_CLKDIV;
  231. #endif
  232. #if CONFIG_SYS_MAX_I2C_BUS > 1
  233. case 1:
  234. return (struct twi_regs *)TWI1_CLKDIV;
  235. #endif
  236. case 0:
  237. return (struct twi_regs *)TWI0_CLKDIV;
  238. default:
  239. printf("wrong hwadapnr: %d\n", adap->hwadapnr);
  240. }
  241. return NULL;
  242. }
  243. U_BOOT_I2C_ADAP_COMPLETE(adi_i2c0, adi_i2c_init, adi_i2c_probe,
  244. adi_i2c_read, adi_i2c_write,
  245. adi_i2c_setspeed,
  246. CONFIG_SYS_I2C_SPEED,
  247. 0,
  248. 0)
  249. #if CONFIG_SYS_MAX_I2C_BUS > 1
  250. U_BOOT_I2C_ADAP_COMPLETE(adi_i2c1, adi_i2c_init, adi_i2c_probe,
  251. adi_i2c_read, adi_i2c_write,
  252. adi_i2c_setspeed,
  253. CONFIG_SYS_I2C_SPEED,
  254. 0,
  255. 1)
  256. #endif
  257. #if CONFIG_SYS_MAX_I2C_BUS > 2
  258. U_BOOT_I2C_ADAP_COMPLETE(adi_i2c2, adi_i2c_init, adi_i2c_probe,
  259. adi_i2c_read, adi_i2c_write,
  260. adi_i2c_setspeed,
  261. CONFIG_SYS_I2C_SPEED,
  262. 0,
  263. 2)
  264. #endif