clock-tables.h 4.0 KB

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  1. /*
  2. * Copyright (c) 2011 The Chromium OS Authors.
  3. * Copyright (c) 2010-2012 NVIDIA Corporation <www.nvidia.com>
  4. * See file CREDITS for list of people who contributed to this
  5. * project.
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation; either version 2 of
  10. * the License, or (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20. * MA 02111-1307 USA
  21. */
  22. /* Tegra20 clock PLL tables */
  23. #ifndef _CLOCK_TABLES_H_
  24. #define _CLOCK_TABLES_H_
  25. /* The PLLs supported by the hardware */
  26. enum clock_id {
  27. CLOCK_ID_FIRST,
  28. CLOCK_ID_CGENERAL = CLOCK_ID_FIRST,
  29. CLOCK_ID_MEMORY,
  30. CLOCK_ID_PERIPH,
  31. CLOCK_ID_AUDIO,
  32. CLOCK_ID_USB,
  33. CLOCK_ID_DISPLAY,
  34. /* now the simple ones */
  35. CLOCK_ID_FIRST_SIMPLE,
  36. CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE,
  37. CLOCK_ID_EPCI,
  38. CLOCK_ID_SFROM32KHZ,
  39. /* These are the base clocks (inputs to the Tegra SOC) */
  40. CLOCK_ID_32KHZ,
  41. CLOCK_ID_OSC,
  42. CLOCK_ID_COUNT, /* number of clocks */
  43. CLOCK_ID_NONE = -1,
  44. };
  45. /* The clocks supported by the hardware */
  46. enum periph_id {
  47. PERIPH_ID_FIRST,
  48. /* Low word: 31:0 */
  49. PERIPH_ID_CPU = PERIPH_ID_FIRST,
  50. PERIPH_ID_RESERVED1,
  51. PERIPH_ID_RESERVED2,
  52. PERIPH_ID_AC97,
  53. PERIPH_ID_RTC,
  54. PERIPH_ID_TMR,
  55. PERIPH_ID_UART1,
  56. PERIPH_ID_UART2,
  57. /* 8 */
  58. PERIPH_ID_GPIO,
  59. PERIPH_ID_SDMMC2,
  60. PERIPH_ID_SPDIF,
  61. PERIPH_ID_I2S1,
  62. PERIPH_ID_I2C1,
  63. PERIPH_ID_NDFLASH,
  64. PERIPH_ID_SDMMC1,
  65. PERIPH_ID_SDMMC4,
  66. /* 16 */
  67. PERIPH_ID_TWC,
  68. PERIPH_ID_PWM,
  69. PERIPH_ID_I2S2,
  70. PERIPH_ID_EPP,
  71. PERIPH_ID_VI,
  72. PERIPH_ID_2D,
  73. PERIPH_ID_USBD,
  74. PERIPH_ID_ISP,
  75. /* 24 */
  76. PERIPH_ID_3D,
  77. PERIPH_ID_IDE,
  78. PERIPH_ID_DISP2,
  79. PERIPH_ID_DISP1,
  80. PERIPH_ID_HOST1X,
  81. PERIPH_ID_VCP,
  82. PERIPH_ID_RESERVED30,
  83. PERIPH_ID_CACHE2,
  84. /* Middle word: 63:32 */
  85. PERIPH_ID_MEM,
  86. PERIPH_ID_AHBDMA,
  87. PERIPH_ID_APBDMA,
  88. PERIPH_ID_RESERVED35,
  89. PERIPH_ID_KBC,
  90. PERIPH_ID_STAT_MON,
  91. PERIPH_ID_PMC,
  92. PERIPH_ID_FUSE,
  93. /* 40 */
  94. PERIPH_ID_KFUSE,
  95. PERIPH_ID_SBC1,
  96. PERIPH_ID_SNOR,
  97. PERIPH_ID_SPI1,
  98. PERIPH_ID_SBC2,
  99. PERIPH_ID_XIO,
  100. PERIPH_ID_SBC3,
  101. PERIPH_ID_DVC_I2C,
  102. /* 48 */
  103. PERIPH_ID_DSI,
  104. PERIPH_ID_TVO,
  105. PERIPH_ID_MIPI,
  106. PERIPH_ID_HDMI,
  107. PERIPH_ID_CSI,
  108. PERIPH_ID_TVDAC,
  109. PERIPH_ID_I2C2,
  110. PERIPH_ID_UART3,
  111. /* 56 */
  112. PERIPH_ID_RESERVED56,
  113. PERIPH_ID_EMC,
  114. PERIPH_ID_USB2,
  115. PERIPH_ID_USB3,
  116. PERIPH_ID_MPE,
  117. PERIPH_ID_VDE,
  118. PERIPH_ID_BSEA,
  119. PERIPH_ID_BSEV,
  120. /* Upper word 95:64 */
  121. PERIPH_ID_SPEEDO,
  122. PERIPH_ID_UART4,
  123. PERIPH_ID_UART5,
  124. PERIPH_ID_I2C3,
  125. PERIPH_ID_SBC4,
  126. PERIPH_ID_SDMMC3,
  127. PERIPH_ID_PCIE,
  128. PERIPH_ID_OWR,
  129. /* 72 */
  130. PERIPH_ID_AFI,
  131. PERIPH_ID_CORESIGHT,
  132. PERIPH_ID_RESERVED74,
  133. PERIPH_ID_AVPUCQ,
  134. PERIPH_ID_RESERVED76,
  135. PERIPH_ID_RESERVED77,
  136. PERIPH_ID_RESERVED78,
  137. PERIPH_ID_RESERVED79,
  138. /* 80 */
  139. PERIPH_ID_RESERVED80,
  140. PERIPH_ID_RESERVED81,
  141. PERIPH_ID_RESERVED82,
  142. PERIPH_ID_RESERVED83,
  143. PERIPH_ID_IRAMA,
  144. PERIPH_ID_IRAMB,
  145. PERIPH_ID_IRAMC,
  146. PERIPH_ID_IRAMD,
  147. /* 88 */
  148. PERIPH_ID_CRAM2,
  149. PERIPH_ID_SYNC_CLK_DOUBLER,
  150. PERIPH_ID_CLK_M_DOUBLER,
  151. PERIPH_ID_RESERVED91,
  152. PERIPH_ID_SUS_OUT,
  153. PERIPH_ID_DEV2_OUT,
  154. PERIPH_ID_DEV1_OUT,
  155. PERIPH_ID_COUNT,
  156. PERIPH_ID_NONE = -1,
  157. };
  158. enum pll_out_id {
  159. PLL_OUT1,
  160. PLL_OUT2,
  161. PLL_OUT3,
  162. PLL_OUT4
  163. };
  164. /* Converts a clock number to a clock register: 0=L, 1=H, 2=U */
  165. #define PERIPH_REG(id) ((id) >> 5)
  166. /* Mask value for a clock (within PERIPH_REG(id)) */
  167. #define PERIPH_MASK(id) (1 << ((id) & 0x1f))
  168. /* return 1 if a PLL ID is in range, and not a simple PLL */
  169. #define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && \
  170. (id) < CLOCK_ID_FIRST_SIMPLE)
  171. /* return 1 if a peripheral ID is in range */
  172. #define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \
  173. (id) < PERIPH_ID_COUNT)
  174. #endif /* _CLOCK_TABLES_H_ */