mxc_gpio.c 8.0 KB

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  1. /*
  2. * Copyright (C) 2009
  3. * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
  4. *
  5. * Copyright (C) 2011
  6. * Stefano Babic, DENX Software Engineering, <sbabic@denx.de>
  7. *
  8. * SPDX-License-Identifier: GPL-2.0+
  9. */
  10. #include <common.h>
  11. #include <errno.h>
  12. #include <dm.h>
  13. #include <malloc.h>
  14. #include <asm/arch/imx-regs.h>
  15. #include <asm/gpio.h>
  16. #include <asm/io.h>
  17. enum mxc_gpio_direction {
  18. MXC_GPIO_DIRECTION_IN,
  19. MXC_GPIO_DIRECTION_OUT,
  20. };
  21. #define GPIO_PER_BANK 32
  22. struct mxc_gpio_plat {
  23. int bank_index;
  24. struct gpio_regs *regs;
  25. };
  26. struct mxc_bank_info {
  27. struct gpio_regs *regs;
  28. };
  29. #ifndef CONFIG_DM_GPIO
  30. #define GPIO_TO_PORT(n) (n / 32)
  31. /* GPIO port description */
  32. static unsigned long gpio_ports[] = {
  33. [0] = GPIO1_BASE_ADDR,
  34. [1] = GPIO2_BASE_ADDR,
  35. [2] = GPIO3_BASE_ADDR,
  36. #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
  37. defined(CONFIG_MX53) || defined(CONFIG_MX6)
  38. [3] = GPIO4_BASE_ADDR,
  39. #endif
  40. #if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6)
  41. [4] = GPIO5_BASE_ADDR,
  42. #ifndef CONFIG_MX6UL
  43. [5] = GPIO6_BASE_ADDR,
  44. #endif
  45. #endif
  46. #if defined(CONFIG_MX53) || defined(CONFIG_MX6)
  47. #ifndef CONFIG_MX6UL
  48. [6] = GPIO7_BASE_ADDR,
  49. #endif
  50. #endif
  51. };
  52. static int mxc_gpio_direction(unsigned int gpio,
  53. enum mxc_gpio_direction direction)
  54. {
  55. unsigned int port = GPIO_TO_PORT(gpio);
  56. struct gpio_regs *regs;
  57. u32 l;
  58. if (port >= ARRAY_SIZE(gpio_ports))
  59. return -1;
  60. gpio &= 0x1f;
  61. regs = (struct gpio_regs *)gpio_ports[port];
  62. l = readl(&regs->gpio_dir);
  63. switch (direction) {
  64. case MXC_GPIO_DIRECTION_OUT:
  65. l |= 1 << gpio;
  66. break;
  67. case MXC_GPIO_DIRECTION_IN:
  68. l &= ~(1 << gpio);
  69. }
  70. writel(l, &regs->gpio_dir);
  71. return 0;
  72. }
  73. int gpio_set_value(unsigned gpio, int value)
  74. {
  75. unsigned int port = GPIO_TO_PORT(gpio);
  76. struct gpio_regs *regs;
  77. u32 l;
  78. if (port >= ARRAY_SIZE(gpio_ports))
  79. return -1;
  80. gpio &= 0x1f;
  81. regs = (struct gpio_regs *)gpio_ports[port];
  82. l = readl(&regs->gpio_dr);
  83. if (value)
  84. l |= 1 << gpio;
  85. else
  86. l &= ~(1 << gpio);
  87. writel(l, &regs->gpio_dr);
  88. return 0;
  89. }
  90. int gpio_get_value(unsigned gpio)
  91. {
  92. unsigned int port = GPIO_TO_PORT(gpio);
  93. struct gpio_regs *regs;
  94. u32 val;
  95. if (port >= ARRAY_SIZE(gpio_ports))
  96. return -1;
  97. gpio &= 0x1f;
  98. regs = (struct gpio_regs *)gpio_ports[port];
  99. val = (readl(&regs->gpio_psr) >> gpio) & 0x01;
  100. return val;
  101. }
  102. int gpio_request(unsigned gpio, const char *label)
  103. {
  104. unsigned int port = GPIO_TO_PORT(gpio);
  105. if (port >= ARRAY_SIZE(gpio_ports))
  106. return -1;
  107. return 0;
  108. }
  109. int gpio_free(unsigned gpio)
  110. {
  111. return 0;
  112. }
  113. int gpio_direction_input(unsigned gpio)
  114. {
  115. return mxc_gpio_direction(gpio, MXC_GPIO_DIRECTION_IN);
  116. }
  117. int gpio_direction_output(unsigned gpio, int value)
  118. {
  119. int ret = gpio_set_value(gpio, value);
  120. if (ret < 0)
  121. return ret;
  122. return mxc_gpio_direction(gpio, MXC_GPIO_DIRECTION_OUT);
  123. }
  124. #endif
  125. #ifdef CONFIG_DM_GPIO
  126. #include <fdtdec.h>
  127. DECLARE_GLOBAL_DATA_PTR;
  128. static int mxc_gpio_is_output(struct gpio_regs *regs, int offset)
  129. {
  130. u32 val;
  131. val = readl(&regs->gpio_dir);
  132. return val & (1 << offset) ? 1 : 0;
  133. }
  134. static void mxc_gpio_bank_direction(struct gpio_regs *regs, int offset,
  135. enum mxc_gpio_direction direction)
  136. {
  137. u32 l;
  138. l = readl(&regs->gpio_dir);
  139. switch (direction) {
  140. case MXC_GPIO_DIRECTION_OUT:
  141. l |= 1 << offset;
  142. break;
  143. case MXC_GPIO_DIRECTION_IN:
  144. l &= ~(1 << offset);
  145. }
  146. writel(l, &regs->gpio_dir);
  147. }
  148. static void mxc_gpio_bank_set_value(struct gpio_regs *regs, int offset,
  149. int value)
  150. {
  151. u32 l;
  152. l = readl(&regs->gpio_dr);
  153. if (value)
  154. l |= 1 << offset;
  155. else
  156. l &= ~(1 << offset);
  157. writel(l, &regs->gpio_dr);
  158. }
  159. static int mxc_gpio_bank_get_value(struct gpio_regs *regs, int offset)
  160. {
  161. return (readl(&regs->gpio_psr) >> offset) & 0x01;
  162. }
  163. /* set GPIO pin 'gpio' as an input */
  164. static int mxc_gpio_direction_input(struct udevice *dev, unsigned offset)
  165. {
  166. struct mxc_bank_info *bank = dev_get_priv(dev);
  167. /* Configure GPIO direction as input. */
  168. mxc_gpio_bank_direction(bank->regs, offset, MXC_GPIO_DIRECTION_IN);
  169. return 0;
  170. }
  171. /* set GPIO pin 'gpio' as an output, with polarity 'value' */
  172. static int mxc_gpio_direction_output(struct udevice *dev, unsigned offset,
  173. int value)
  174. {
  175. struct mxc_bank_info *bank = dev_get_priv(dev);
  176. /* Configure GPIO output value. */
  177. mxc_gpio_bank_set_value(bank->regs, offset, value);
  178. /* Configure GPIO direction as output. */
  179. mxc_gpio_bank_direction(bank->regs, offset, MXC_GPIO_DIRECTION_OUT);
  180. return 0;
  181. }
  182. /* read GPIO IN value of pin 'gpio' */
  183. static int mxc_gpio_get_value(struct udevice *dev, unsigned offset)
  184. {
  185. struct mxc_bank_info *bank = dev_get_priv(dev);
  186. return mxc_gpio_bank_get_value(bank->regs, offset);
  187. }
  188. /* write GPIO OUT value to pin 'gpio' */
  189. static int mxc_gpio_set_value(struct udevice *dev, unsigned offset,
  190. int value)
  191. {
  192. struct mxc_bank_info *bank = dev_get_priv(dev);
  193. mxc_gpio_bank_set_value(bank->regs, offset, value);
  194. return 0;
  195. }
  196. static int mxc_gpio_get_function(struct udevice *dev, unsigned offset)
  197. {
  198. struct mxc_bank_info *bank = dev_get_priv(dev);
  199. /* GPIOF_FUNC is not implemented yet */
  200. if (mxc_gpio_is_output(bank->regs, offset))
  201. return GPIOF_OUTPUT;
  202. else
  203. return GPIOF_INPUT;
  204. }
  205. static const struct dm_gpio_ops gpio_mxc_ops = {
  206. .direction_input = mxc_gpio_direction_input,
  207. .direction_output = mxc_gpio_direction_output,
  208. .get_value = mxc_gpio_get_value,
  209. .set_value = mxc_gpio_set_value,
  210. .get_function = mxc_gpio_get_function,
  211. };
  212. static int mxc_gpio_probe(struct udevice *dev)
  213. {
  214. struct mxc_bank_info *bank = dev_get_priv(dev);
  215. struct mxc_gpio_plat *plat = dev_get_platdata(dev);
  216. struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
  217. int banknum;
  218. char name[18], *str;
  219. banknum = plat->bank_index;
  220. sprintf(name, "GPIO%d_", banknum + 1);
  221. str = strdup(name);
  222. if (!str)
  223. return -ENOMEM;
  224. uc_priv->bank_name = str;
  225. uc_priv->gpio_count = GPIO_PER_BANK;
  226. bank->regs = plat->regs;
  227. return 0;
  228. }
  229. static int mxc_gpio_bind(struct udevice *dev)
  230. {
  231. struct mxc_gpio_plat *plat = dev->platdata;
  232. fdt_addr_t addr;
  233. /*
  234. * If platdata already exsits, directly return.
  235. * Actually only when DT is not supported, platdata
  236. * is statically initialized in U_BOOT_DEVICES.Here
  237. * will return.
  238. */
  239. if (plat)
  240. return 0;
  241. addr = dev_get_addr(dev);
  242. if (addr == FDT_ADDR_T_NONE)
  243. return -ENODEV;
  244. /*
  245. * TODO:
  246. * When every board is converted to driver model and DT is supported,
  247. * this can be done by auto-alloc feature, but not using calloc
  248. * to alloc memory for platdata.
  249. */
  250. plat = calloc(1, sizeof(*plat));
  251. if (!plat)
  252. return -ENOMEM;
  253. plat->regs = (struct gpio_regs *)addr;
  254. plat->bank_index = dev->req_seq;
  255. dev->platdata = plat;
  256. return 0;
  257. }
  258. static const struct udevice_id mxc_gpio_ids[] = {
  259. { .compatible = "fsl,imx35-gpio" },
  260. { }
  261. };
  262. U_BOOT_DRIVER(gpio_mxc) = {
  263. .name = "gpio_mxc",
  264. .id = UCLASS_GPIO,
  265. .ops = &gpio_mxc_ops,
  266. .probe = mxc_gpio_probe,
  267. .priv_auto_alloc_size = sizeof(struct mxc_bank_info),
  268. .of_match = mxc_gpio_ids,
  269. .bind = mxc_gpio_bind,
  270. };
  271. #ifndef CONFIG_OF_CONTROL
  272. static const struct mxc_gpio_plat mxc_plat[] = {
  273. { 0, (struct gpio_regs *)GPIO1_BASE_ADDR },
  274. { 1, (struct gpio_regs *)GPIO2_BASE_ADDR },
  275. { 2, (struct gpio_regs *)GPIO3_BASE_ADDR },
  276. #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
  277. defined(CONFIG_MX53) || defined(CONFIG_MX6)
  278. { 3, (struct gpio_regs *)GPIO4_BASE_ADDR },
  279. #endif
  280. #if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6)
  281. { 4, (struct gpio_regs *)GPIO5_BASE_ADDR },
  282. { 5, (struct gpio_regs *)GPIO6_BASE_ADDR },
  283. #endif
  284. #if defined(CONFIG_MX53) || defined(CONFIG_MX6)
  285. { 6, (struct gpio_regs *)GPIO7_BASE_ADDR },
  286. #endif
  287. };
  288. U_BOOT_DEVICES(mxc_gpios) = {
  289. { "gpio_mxc", &mxc_plat[0] },
  290. { "gpio_mxc", &mxc_plat[1] },
  291. { "gpio_mxc", &mxc_plat[2] },
  292. #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
  293. defined(CONFIG_MX53) || defined(CONFIG_MX6)
  294. { "gpio_mxc", &mxc_plat[3] },
  295. #endif
  296. #if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6)
  297. { "gpio_mxc", &mxc_plat[4] },
  298. { "gpio_mxc", &mxc_plat[5] },
  299. #endif
  300. #if defined(CONFIG_MX53) || defined(CONFIG_MX6)
  301. { "gpio_mxc", &mxc_plat[6] },
  302. #endif
  303. };
  304. #endif
  305. #endif