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arch
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powerpc
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cpu
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mpc8xx
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kgdb.S

kgdb.S 911 B
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  1. /*
    2. 

  2.  *  Copyright (C) 2000	Murray Jensen <Murray.Jensen@cmst.csiro.au>
    3. 

  3.  *
    4. 

  4.  * SPDX-License-Identifier:	GPL-2.0+
    5. 

  5.  */
    6. 

  6. 

  7. #include <config.h>
    8. 

  8. #include <command.h>
    9. 

  9. #include <mpc8xx.h>
    10. 

  10. #include <version.h>
    11. 

  11. 

  12. #include <ppc_asm.tmpl>
    13. 

  13. #include <ppc_defs.h>
    14. 

  14. 

  15. #include <asm/cache.h>
    16. 

  16. #include <asm/mmu.h>
    17. 

  17. 

  18. #if defined(CONFIG_CMD_KGDB)
    19. 

  19. 

  20.  /*
    21. 

  21.  * cache flushing routines for kgdb
    22. 

  22.  */
    23. 

  23. 

  24. 	.globl	kgdb_flush_cache_all
    25. 

  25. kgdb_flush_cache_all:
    26. 

  26. 	lis	r3, IDC_INVALL@h
    27. 

  27. 	mtspr	DC_CST, r3
    28. 

  28. 	sync
    29. 

  29. 	lis	r3, IDC_INVALL@h
    30. 

  30. 	mtspr	IC_CST, r3
    31. 

  31. 	SYNC
    32. 

  32. 	blr
    33. 

  33. 

  34. 	.globl	kgdb_flush_cache_range
    35. 

  35. kgdb_flush_cache_range:
    36. 

  36. 	li	r5,CONFIG_SYS_CACHELINE_SIZE-1
    37. 

  37. 	andc	r3,r3,r5
    38. 

  38. 	subf	r4,r3,r4
    39. 

  39. 	add	r4,r4,r5
    40. 

  40. 	srwi.	r4,r4,CONFIG_SYS_CACHELINE_SHIFT
    41. 

  41. 	beqlr
    42. 

  42. 	mtctr	r4
    43. 

  43. 	mr	r6,r3
    44. 

  44. 1:	dcbst	0,r3
    45. 

  45. 	addi	r3,r3,CONFIG_SYS_CACHELINE_SIZE
    46. 

  46. 	bdnz	1b
    47. 

  47. 	sync				/* wait for dcbst's to get to ram */
    48. 

  48. 	mtctr	r4
    49. 

  49. 2:	icbi	0,r6
    50. 

  50. 	addi	r6,r6,CONFIG_SYS_CACHELINE_SIZE
    51. 

  51. 	bdnz	2b
    52. 

  52. 	SYNC
    53. 

  53. 	blr
    54. 

  54. 

  55. #endif
    56.