p1021_serdes.c 2.6 KB

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  1. /*
  2. * Copyright 2010-2011 Freescale Semiconductor, Inc.
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #include <config.h>
  7. #include <common.h>
  8. #include <asm/io.h>
  9. #include <asm/immap_85xx.h>
  10. #include <asm/fsl_serdes.h>
  11. typedef struct serdes_85xx {
  12. u32 srdscr0; /* 0x00 - SRDS Control Register 0 */
  13. u32 srdscr1; /* 0x04 - SRDS Control Register 1 */
  14. u32 srdscr2; /* 0x08 - SRDS Control Register 2 */
  15. u32 srdscr3; /* 0x0C - SRDS Control Register 3 */
  16. u32 srdscr4; /* 0x10 - SRDS Control Register 4 */
  17. } serdes_85xx_t;
  18. #define FSL_SRDSCR3_EIC0(x) (((x) & 0x1f) << 8)
  19. #define FSL_SRDSCR3_EIC0_MASK FSL_SRDSCR3_EIC0(0x1f)
  20. #define FSL_SRDSCR3_EIC1(x) (((x) & 0x1f) << 0)
  21. #define FSL_SRDSCR3_EIC1_MASK FSL_SRDSCR3_EIC1(0x1f)
  22. #define FSL_SRDSCR4_EIC2(x) (((x) & 0x1f) << 8)
  23. #define FSL_SRDSCR4_EIC2_MASK FSL_SRDSCR4_EIC2(0x1f)
  24. #define FSL_SRDSCR4_EIC3(x) (((x) & 0x1f) << 0)
  25. #define FSL_SRDSCR4_EIC3_MASK FSL_SRDSCR4_EIC3(0x1f)
  26. #define EIC_PCIE 0x13
  27. #define EIC_SGMII 0x04
  28. #define SRDS1_MAX_LANES 4
  29. static u32 serdes1_prtcl_map;
  30. static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
  31. [0x0] = {PCIE1, NONE, NONE, NONE},
  32. [0x6] = {PCIE1, PCIE1, PCIE1, PCIE1},
  33. [0xe] = {PCIE1, PCIE2, SGMII_TSEC2, SGMII_TSEC3},
  34. [0xf] = {PCIE1, PCIE1, SGMII_TSEC2, SGMII_TSEC3},
  35. };
  36. int is_serdes_configured(enum srds_prtcl prtcl)
  37. {
  38. return (1 << prtcl) & serdes1_prtcl_map;
  39. }
  40. void fsl_serdes_init(void)
  41. {
  42. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  43. serdes_85xx_t *serdes = (void *)CONFIG_SYS_MPC85xx_SERDES1_ADDR;
  44. u32 pordevsr = in_be32(&gur->pordevsr);
  45. u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
  46. MPC85xx_PORDEVSR_IO_SEL_SHIFT;
  47. int lane;
  48. u32 mask, val;
  49. debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
  50. if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
  51. printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
  52. return;
  53. }
  54. for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
  55. enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
  56. serdes1_prtcl_map |= (1 << lane_prtcl);
  57. }
  58. /* Init SERDES Receiver electrical idle detection control for PCIe */
  59. /* Lane 0 is always PCIe 1 */
  60. mask = FSL_SRDSCR3_EIC0_MASK;
  61. val = FSL_SRDSCR3_EIC0(EIC_PCIE);
  62. /* Lane 1 */
  63. if ((serdes1_cfg_tbl[srds_cfg][1] == PCIE1) ||
  64. (serdes1_cfg_tbl[srds_cfg][1] == PCIE2)) {
  65. mask |= FSL_SRDSCR3_EIC1_MASK;
  66. val |= FSL_SRDSCR3_EIC1(EIC_PCIE);
  67. }
  68. /* Handle lanes 0 & 1 */
  69. clrsetbits_be32(&serdes->srdscr3, mask, val);
  70. /* Handle lanes 2 & 3 */
  71. if (srds_cfg == 0x6) {
  72. mask = FSL_SRDSCR4_EIC2_MASK | FSL_SRDSCR4_EIC3_MASK;
  73. val = FSL_SRDSCR4_EIC2(EIC_PCIE) | FSL_SRDSCR4_EIC3(EIC_PCIE);
  74. clrsetbits_be32(&serdes->srdscr4, mask, val);
  75. }
  76. /* 100 ms delay */
  77. udelay(100000);
  78. }