mpc8536_serdes.c 6.9 KB

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  1. /*
  2. * Copyright 2008,2010 Freescale Semiconductor, Inc.
  3. * Dave Liu <daveliu@freescale.com>
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. #include <config.h>
  8. #include <common.h>
  9. #include <asm/io.h>
  10. #include <asm/immap_85xx.h>
  11. #include <asm/fsl_serdes.h>
  12. /* PORDEVSR register */
  13. #define GUTS_PORDEVSR_OFFS 0xc
  14. #define GUTS_PORDEVSR_SERDES2_IO_SEL 0x38000000
  15. #define GUTS_PORDEVSR_SERDES2_IO_SEL_SHIFT 27
  16. /* SerDes CR0 register */
  17. #define FSL_SRDSCR0_OFFS 0x0
  18. #define FSL_SRDSCR0_TXEQA_MASK 0x00007000
  19. #define FSL_SRDSCR0_TXEQA_SGMII 0x00004000
  20. #define FSL_SRDSCR0_TXEQA_SATA 0x00001000
  21. #define FSL_SRDSCR0_TXEQE_MASK 0x00000700
  22. #define FSL_SRDSCR0_TXEQE_SGMII 0x00000400
  23. #define FSL_SRDSCR0_TXEQE_SATA 0x00000100
  24. /* SerDes CR1 register */
  25. #define FSL_SRDSCR1_OFFS 0x4
  26. #define FSL_SRDSCR1_LANEA_MASK 0x80200000
  27. #define FSL_SRDSCR1_LANEA_OFF 0x80200000
  28. #define FSL_SRDSCR1_LANEE_MASK 0x08020000
  29. #define FSL_SRDSCR1_LANEE_OFF 0x08020000
  30. /* SerDes CR2 register */
  31. #define FSL_SRDSCR2_OFFS 0x8
  32. #define FSL_SRDSCR2_EICA_MASK 0x00001f00
  33. #define FSL_SRDSCR2_EICA_SGMII 0x00000400
  34. #define FSL_SRDSCR2_EICA_SATA 0x00001400
  35. #define FSL_SRDSCR2_EICE_MASK 0x0000001f
  36. #define FSL_SRDSCR2_EICE_SGMII 0x00000004
  37. #define FSL_SRDSCR2_EICE_SATA 0x00000014
  38. /* SerDes CR3 register */
  39. #define FSL_SRDSCR3_OFFS 0xc
  40. #define FSL_SRDSCR3_LANEA_MASK 0x3f000700
  41. #define FSL_SRDSCR3_LANEA_SGMII 0x00000000
  42. #define FSL_SRDSCR3_LANEA_SATA 0x15000500
  43. #define FSL_SRDSCR3_LANEE_MASK 0x003f0007
  44. #define FSL_SRDSCR3_LANEE_SGMII 0x00000000
  45. #define FSL_SRDSCR3_LANEE_SATA 0x00150005
  46. #define SRDS1_MAX_LANES 8
  47. #define SRDS2_MAX_LANES 2
  48. static u32 serdes1_prtcl_map, serdes2_prtcl_map;
  49. static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
  50. [0x2] = {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, NONE, NONE},
  51. [0x3] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1},
  52. [0x5] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2},
  53. [0x7] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE3, PCIE3},
  54. };
  55. static u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
  56. [0x1] = {SATA1, SATA2},
  57. [0x3] = {SATA1, NONE},
  58. [0x4] = {SGMII_TSEC1, SGMII_TSEC3},
  59. [0x6] = {SGMII_TSEC1, NONE},
  60. };
  61. int is_serdes_configured(enum srds_prtcl device)
  62. {
  63. int ret = (1 << device) & serdes1_prtcl_map;
  64. if (ret)
  65. return ret;
  66. return (1 << device) & serdes2_prtcl_map;
  67. }
  68. void fsl_serdes_init(void)
  69. {
  70. void *guts = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  71. void *sd = (void *)CONFIG_SYS_MPC85xx_SERDES2_ADDR;
  72. u32 pordevsr = in_be32(guts + GUTS_PORDEVSR_OFFS);
  73. u32 srds1_io_sel, srds2_io_sel;
  74. u32 tmp;
  75. int lane;
  76. srds1_io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
  77. MPC85xx_PORDEVSR_IO_SEL_SHIFT;
  78. /* parse the SRDS2_IO_SEL of PORDEVSR */
  79. srds2_io_sel = (pordevsr & GUTS_PORDEVSR_SERDES2_IO_SEL)
  80. >> GUTS_PORDEVSR_SERDES2_IO_SEL_SHIFT;
  81. debug("PORDEVSR[SRDS1_IO_SEL] = %x\n", srds1_io_sel);
  82. debug("PORDEVSR[SRDS2_IO_SEL] = %x\n", srds2_io_sel);
  83. switch (srds2_io_sel) {
  84. case 1: /* Lane A - SATA1, Lane E - SATA2 */
  85. /* CR 0 */
  86. tmp = in_be32(sd + FSL_SRDSCR0_OFFS);
  87. tmp &= ~FSL_SRDSCR0_TXEQA_MASK;
  88. tmp |= FSL_SRDSCR0_TXEQA_SATA;
  89. tmp &= ~FSL_SRDSCR0_TXEQE_MASK;
  90. tmp |= FSL_SRDSCR0_TXEQE_SATA;
  91. out_be32(sd + FSL_SRDSCR0_OFFS, tmp);
  92. /* CR 1 */
  93. tmp = in_be32(sd + FSL_SRDSCR1_OFFS);
  94. tmp &= ~FSL_SRDSCR1_LANEA_MASK;
  95. tmp &= ~FSL_SRDSCR1_LANEE_MASK;
  96. out_be32(sd + FSL_SRDSCR1_OFFS, tmp);
  97. /* CR 2 */
  98. tmp = in_be32(sd + FSL_SRDSCR2_OFFS);
  99. tmp &= ~FSL_SRDSCR2_EICA_MASK;
  100. tmp |= FSL_SRDSCR2_EICA_SATA;
  101. tmp &= ~FSL_SRDSCR2_EICE_MASK;
  102. tmp |= FSL_SRDSCR2_EICE_SATA;
  103. out_be32(sd + FSL_SRDSCR2_OFFS, tmp);
  104. /* CR 3 */
  105. tmp = in_be32(sd + FSL_SRDSCR3_OFFS);
  106. tmp &= ~FSL_SRDSCR3_LANEA_MASK;
  107. tmp |= FSL_SRDSCR3_LANEA_SATA;
  108. tmp &= ~FSL_SRDSCR3_LANEE_MASK;
  109. tmp |= FSL_SRDSCR3_LANEE_SATA;
  110. out_be32(sd + FSL_SRDSCR3_OFFS, tmp);
  111. break;
  112. case 3: /* Lane A - SATA1, Lane E - disabled */
  113. /* CR 0 */
  114. tmp = in_be32(sd + FSL_SRDSCR0_OFFS);
  115. tmp &= ~FSL_SRDSCR0_TXEQA_MASK;
  116. tmp |= FSL_SRDSCR0_TXEQA_SATA;
  117. out_be32(sd + FSL_SRDSCR0_OFFS, tmp);
  118. /* CR 1 */
  119. tmp = in_be32(sd + FSL_SRDSCR1_OFFS);
  120. tmp &= ~FSL_SRDSCR1_LANEE_MASK;
  121. tmp |= FSL_SRDSCR1_LANEE_OFF;
  122. out_be32(sd + FSL_SRDSCR1_OFFS, tmp);
  123. /* CR 2 */
  124. tmp = in_be32(sd + FSL_SRDSCR2_OFFS);
  125. tmp &= ~FSL_SRDSCR2_EICA_MASK;
  126. tmp |= FSL_SRDSCR2_EICA_SATA;
  127. out_be32(sd + FSL_SRDSCR2_OFFS, tmp);
  128. /* CR 3 */
  129. tmp = in_be32(sd + FSL_SRDSCR3_OFFS);
  130. tmp &= ~FSL_SRDSCR3_LANEA_MASK;
  131. tmp |= FSL_SRDSCR3_LANEA_SATA;
  132. out_be32(sd + FSL_SRDSCR3_OFFS, tmp);
  133. break;
  134. case 4: /* Lane A - eTSEC1 SGMII, Lane E - eTSEC3 SGMII */
  135. /* CR 0 */
  136. tmp = in_be32(sd + FSL_SRDSCR0_OFFS);
  137. tmp &= ~FSL_SRDSCR0_TXEQA_MASK;
  138. tmp |= FSL_SRDSCR0_TXEQA_SGMII;
  139. tmp &= ~FSL_SRDSCR0_TXEQE_MASK;
  140. tmp |= FSL_SRDSCR0_TXEQE_SGMII;
  141. out_be32(sd + FSL_SRDSCR0_OFFS, tmp);
  142. /* CR 1 */
  143. tmp = in_be32(sd + FSL_SRDSCR1_OFFS);
  144. tmp &= ~FSL_SRDSCR1_LANEA_MASK;
  145. tmp &= ~FSL_SRDSCR1_LANEE_MASK;
  146. out_be32(sd + FSL_SRDSCR1_OFFS, tmp);
  147. /* CR 2 */
  148. tmp = in_be32(sd + FSL_SRDSCR2_OFFS);
  149. tmp &= ~FSL_SRDSCR2_EICA_MASK;
  150. tmp |= FSL_SRDSCR2_EICA_SGMII;
  151. tmp &= ~FSL_SRDSCR2_EICE_MASK;
  152. tmp |= FSL_SRDSCR2_EICE_SGMII;
  153. out_be32(sd + FSL_SRDSCR2_OFFS, tmp);
  154. /* CR 3 */
  155. tmp = in_be32(sd + FSL_SRDSCR3_OFFS);
  156. tmp &= ~FSL_SRDSCR3_LANEA_MASK;
  157. tmp |= FSL_SRDSCR3_LANEA_SGMII;
  158. tmp &= ~FSL_SRDSCR3_LANEE_MASK;
  159. tmp |= FSL_SRDSCR3_LANEE_SGMII;
  160. out_be32(sd + FSL_SRDSCR3_OFFS, tmp);
  161. break;
  162. case 6: /* Lane A - eTSEC1 SGMII, Lane E - disabled */
  163. /* CR 0 */
  164. tmp = in_be32(sd + FSL_SRDSCR0_OFFS);
  165. tmp &= ~FSL_SRDSCR0_TXEQA_MASK;
  166. tmp |= FSL_SRDSCR0_TXEQA_SGMII;
  167. out_be32(sd + FSL_SRDSCR0_OFFS, tmp);
  168. /* CR 1 */
  169. tmp = in_be32(sd + FSL_SRDSCR1_OFFS);
  170. tmp &= ~FSL_SRDSCR1_LANEE_MASK;
  171. tmp |= FSL_SRDSCR1_LANEE_OFF;
  172. out_be32(sd + FSL_SRDSCR1_OFFS, tmp);
  173. /* CR 2 */
  174. tmp = in_be32(sd + FSL_SRDSCR2_OFFS);
  175. tmp &= ~FSL_SRDSCR2_EICA_MASK;
  176. tmp |= FSL_SRDSCR2_EICA_SGMII;
  177. out_be32(sd + FSL_SRDSCR2_OFFS, tmp);
  178. /* CR 3 */
  179. tmp = in_be32(sd + FSL_SRDSCR3_OFFS);
  180. tmp &= ~FSL_SRDSCR3_LANEA_MASK;
  181. tmp |= FSL_SRDSCR3_LANEA_SGMII;
  182. out_be32(sd + FSL_SRDSCR3_OFFS, tmp);
  183. break;
  184. case 7: /* Lane A - disabled, Lane E - disabled */
  185. /* CR 1 */
  186. tmp = in_be32(sd + FSL_SRDSCR1_OFFS);
  187. tmp &= ~FSL_SRDSCR1_LANEA_MASK;
  188. tmp |= FSL_SRDSCR1_LANEA_OFF;
  189. tmp &= ~FSL_SRDSCR1_LANEE_MASK;
  190. tmp |= FSL_SRDSCR1_LANEE_OFF;
  191. out_be32(sd + FSL_SRDSCR1_OFFS, tmp);
  192. break;
  193. default:
  194. break;
  195. }
  196. if (srds1_io_sel >= ARRAY_SIZE(serdes1_cfg_tbl)) {
  197. printf("Invalid PORDEVSR[SRDS1_IO_SEL] = %d\n", srds1_io_sel);
  198. return;
  199. }
  200. for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
  201. enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds1_io_sel][lane];
  202. serdes1_prtcl_map |= (1 << lane_prtcl);
  203. }
  204. if (srds2_io_sel >= ARRAY_SIZE(serdes2_cfg_tbl)) {
  205. printf("Invalid PORDEVSR[SRDS2_IO_SEL] = %d\n", srds2_io_sel);
  206. return;
  207. }
  208. for (lane = 0; lane < SRDS2_MAX_LANES; lane++) {
  209. enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds2_io_sel][lane];
  210. serdes2_prtcl_map |= (1 << lane_prtcl);
  211. }
  212. }