pci.c 14 KB

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  1. /*
  2. * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  3. * Andreas Heppel <aheppel@sysgo.de>
  4. *
  5. * (C) Copyright 2002, 2003
  6. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  7. *
  8. * SPDX-License-Identifier: GPL-2.0+
  9. */
  10. /*
  11. * PCI routines
  12. */
  13. #include <common.h>
  14. #include <command.h>
  15. #include <errno.h>
  16. #include <asm/processor.h>
  17. #include <asm/io.h>
  18. #include <pci.h>
  19. DECLARE_GLOBAL_DATA_PTR;
  20. #define PCI_HOSE_OP(rw, size, type) \
  21. int pci_hose_##rw##_config_##size(struct pci_controller *hose, \
  22. pci_dev_t dev, \
  23. int offset, type value) \
  24. { \
  25. return hose->rw##_##size(hose, dev, offset, value); \
  26. }
  27. PCI_HOSE_OP(read, byte, u8 *)
  28. PCI_HOSE_OP(read, word, u16 *)
  29. PCI_HOSE_OP(read, dword, u32 *)
  30. PCI_HOSE_OP(write, byte, u8)
  31. PCI_HOSE_OP(write, word, u16)
  32. PCI_HOSE_OP(write, dword, u32)
  33. #define PCI_OP(rw, size, type, error_code) \
  34. int pci_##rw##_config_##size(pci_dev_t dev, int offset, type value) \
  35. { \
  36. struct pci_controller *hose = pci_bus_to_hose(PCI_BUS(dev)); \
  37. \
  38. if (!hose) \
  39. { \
  40. error_code; \
  41. return -1; \
  42. } \
  43. \
  44. return pci_hose_##rw##_config_##size(hose, dev, offset, value); \
  45. }
  46. PCI_OP(read, byte, u8 *, *value = 0xff)
  47. PCI_OP(read, word, u16 *, *value = 0xffff)
  48. PCI_OP(read, dword, u32 *, *value = 0xffffffff)
  49. PCI_OP(write, byte, u8, )
  50. PCI_OP(write, word, u16, )
  51. PCI_OP(write, dword, u32, )
  52. #define PCI_READ_VIA_DWORD_OP(size, type, off_mask) \
  53. int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose,\
  54. pci_dev_t dev, \
  55. int offset, type val) \
  56. { \
  57. u32 val32; \
  58. \
  59. if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0) { \
  60. *val = -1; \
  61. return -1; \
  62. } \
  63. \
  64. *val = (val32 >> ((offset & (int)off_mask) * 8)); \
  65. \
  66. return 0; \
  67. }
  68. #define PCI_WRITE_VIA_DWORD_OP(size, type, off_mask, val_mask) \
  69. int pci_hose_write_config_##size##_via_dword(struct pci_controller *hose,\
  70. pci_dev_t dev, \
  71. int offset, type val) \
  72. { \
  73. u32 val32, mask, ldata, shift; \
  74. \
  75. if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)\
  76. return -1; \
  77. \
  78. shift = ((offset & (int)off_mask) * 8); \
  79. ldata = (((unsigned long)val) & val_mask) << shift; \
  80. mask = val_mask << shift; \
  81. val32 = (val32 & ~mask) | ldata; \
  82. \
  83. if (pci_hose_write_config_dword(hose, dev, offset & 0xfc, val32) < 0)\
  84. return -1; \
  85. \
  86. return 0; \
  87. }
  88. PCI_READ_VIA_DWORD_OP(byte, u8 *, 0x03)
  89. PCI_READ_VIA_DWORD_OP(word, u16 *, 0x02)
  90. PCI_WRITE_VIA_DWORD_OP(byte, u8, 0x03, 0x000000ff)
  91. PCI_WRITE_VIA_DWORD_OP(word, u16, 0x02, 0x0000ffff)
  92. /*
  93. *
  94. */
  95. static struct pci_controller* hose_head;
  96. struct pci_controller *pci_get_hose_head(void)
  97. {
  98. if (gd->hose)
  99. return gd->hose;
  100. return hose_head;
  101. }
  102. void pci_register_hose(struct pci_controller* hose)
  103. {
  104. struct pci_controller **phose = &hose_head;
  105. while(*phose)
  106. phose = &(*phose)->next;
  107. hose->next = NULL;
  108. *phose = hose;
  109. }
  110. struct pci_controller *pci_bus_to_hose(int bus)
  111. {
  112. struct pci_controller *hose;
  113. for (hose = pci_get_hose_head(); hose; hose = hose->next) {
  114. if (bus >= hose->first_busno && bus <= hose->last_busno)
  115. return hose;
  116. }
  117. printf("pci_bus_to_hose() failed\n");
  118. return NULL;
  119. }
  120. struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr)
  121. {
  122. struct pci_controller *hose;
  123. for (hose = pci_get_hose_head(); hose; hose = hose->next) {
  124. if (hose->cfg_addr == cfg_addr)
  125. return hose;
  126. }
  127. return NULL;
  128. }
  129. int pci_last_busno(void)
  130. {
  131. struct pci_controller *hose = pci_get_hose_head();
  132. if (!hose)
  133. return -1;
  134. while (hose->next)
  135. hose = hose->next;
  136. return hose->last_busno;
  137. }
  138. pci_dev_t pci_find_devices(struct pci_device_id *ids, int index)
  139. {
  140. struct pci_controller * hose;
  141. pci_dev_t bdf;
  142. int bus;
  143. for (hose = pci_get_hose_head(); hose; hose = hose->next) {
  144. #ifdef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE
  145. for (bus = hose->last_busno; bus >= hose->first_busno; bus--) {
  146. #else
  147. for (bus = hose->first_busno; bus <= hose->last_busno; bus++) {
  148. #endif
  149. bdf = pci_hose_find_devices(hose, bus, ids, &index);
  150. if (bdf != -1)
  151. return bdf;
  152. }
  153. }
  154. return -1;
  155. }
  156. int pci_hose_config_device(struct pci_controller *hose,
  157. pci_dev_t dev,
  158. unsigned long io,
  159. pci_addr_t mem,
  160. unsigned long command)
  161. {
  162. u32 bar_response;
  163. unsigned int old_command;
  164. pci_addr_t bar_value;
  165. pci_size_t bar_size;
  166. unsigned char pin;
  167. int bar, found_mem64;
  168. debug("PCI Config: I/O=0x%lx, Memory=0x%llx, Command=0x%lx\n", io,
  169. (u64)mem, command);
  170. pci_hose_write_config_dword(hose, dev, PCI_COMMAND, 0);
  171. for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar += 4) {
  172. pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
  173. pci_hose_read_config_dword(hose, dev, bar, &bar_response);
  174. if (!bar_response)
  175. continue;
  176. found_mem64 = 0;
  177. /* Check the BAR type and set our address mask */
  178. if (bar_response & PCI_BASE_ADDRESS_SPACE) {
  179. bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1;
  180. /* round up region base address to a multiple of size */
  181. io = ((io - 1) | (bar_size - 1)) + 1;
  182. bar_value = io;
  183. /* compute new region base address */
  184. io = io + bar_size;
  185. } else {
  186. if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
  187. PCI_BASE_ADDRESS_MEM_TYPE_64) {
  188. u32 bar_response_upper;
  189. u64 bar64;
  190. pci_hose_write_config_dword(hose, dev, bar + 4,
  191. 0xffffffff);
  192. pci_hose_read_config_dword(hose, dev, bar + 4,
  193. &bar_response_upper);
  194. bar64 = ((u64)bar_response_upper << 32) | bar_response;
  195. bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
  196. found_mem64 = 1;
  197. } else {
  198. bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
  199. }
  200. /* round up region base address to multiple of size */
  201. mem = ((mem - 1) | (bar_size - 1)) + 1;
  202. bar_value = mem;
  203. /* compute new region base address */
  204. mem = mem + bar_size;
  205. }
  206. /* Write it out and update our limit */
  207. pci_hose_write_config_dword (hose, dev, bar, (u32)bar_value);
  208. if (found_mem64) {
  209. bar += 4;
  210. #ifdef CONFIG_SYS_PCI_64BIT
  211. pci_hose_write_config_dword(hose, dev, bar,
  212. (u32)(bar_value >> 32));
  213. #else
  214. pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
  215. #endif
  216. }
  217. }
  218. /* Configure Cache Line Size Register */
  219. pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
  220. /* Configure Latency Timer */
  221. pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
  222. /* Disable interrupt line, if device says it wants to use interrupts */
  223. pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &pin);
  224. if (pin != 0) {
  225. pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
  226. PCI_INTERRUPT_LINE_DISABLE);
  227. }
  228. pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &old_command);
  229. pci_hose_write_config_dword(hose, dev, PCI_COMMAND,
  230. (old_command & 0xffff0000) | command);
  231. return 0;
  232. }
  233. /*
  234. *
  235. */
  236. struct pci_config_table *pci_find_config(struct pci_controller *hose,
  237. unsigned short class,
  238. unsigned int vendor,
  239. unsigned int device,
  240. unsigned int bus,
  241. unsigned int dev,
  242. unsigned int func)
  243. {
  244. struct pci_config_table *table;
  245. for (table = hose->config_table; table && table->vendor; table++) {
  246. if ((table->vendor == PCI_ANY_ID || table->vendor == vendor) &&
  247. (table->device == PCI_ANY_ID || table->device == device) &&
  248. (table->class == PCI_ANY_ID || table->class == class) &&
  249. (table->bus == PCI_ANY_ID || table->bus == bus) &&
  250. (table->dev == PCI_ANY_ID || table->dev == dev) &&
  251. (table->func == PCI_ANY_ID || table->func == func)) {
  252. return table;
  253. }
  254. }
  255. return NULL;
  256. }
  257. void pci_cfgfunc_config_device(struct pci_controller *hose,
  258. pci_dev_t dev,
  259. struct pci_config_table *entry)
  260. {
  261. pci_hose_config_device(hose, dev, entry->priv[0], entry->priv[1],
  262. entry->priv[2]);
  263. }
  264. void pci_cfgfunc_do_nothing(struct pci_controller *hose,
  265. pci_dev_t dev, struct pci_config_table *entry)
  266. {
  267. }
  268. /*
  269. * HJF: Changed this to return int. I think this is required
  270. * to get the correct result when scanning bridges
  271. */
  272. extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
  273. #ifdef CONFIG_PCI_SCAN_SHOW
  274. __weak int pci_print_dev(struct pci_controller *hose, pci_dev_t dev)
  275. {
  276. if (dev == PCI_BDF(hose->first_busno, 0, 0))
  277. return 0;
  278. return 1;
  279. }
  280. #endif /* CONFIG_PCI_SCAN_SHOW */
  281. int pci_hose_scan_bus(struct pci_controller *hose, int bus)
  282. {
  283. unsigned int sub_bus, found_multi = 0;
  284. unsigned short vendor, device, class;
  285. unsigned char header_type;
  286. #ifndef CONFIG_PCI_PNP
  287. struct pci_config_table *cfg;
  288. #endif
  289. pci_dev_t dev;
  290. #ifdef CONFIG_PCI_SCAN_SHOW
  291. static int indent = 0;
  292. #endif
  293. sub_bus = bus;
  294. for (dev = PCI_BDF(bus,0,0);
  295. dev < PCI_BDF(bus, PCI_MAX_PCI_DEVICES - 1,
  296. PCI_MAX_PCI_FUNCTIONS - 1);
  297. dev += PCI_BDF(0, 0, 1)) {
  298. if (pci_skip_dev(hose, dev))
  299. continue;
  300. if (PCI_FUNC(dev) && !found_multi)
  301. continue;
  302. pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
  303. pci_hose_read_config_word(hose, dev, PCI_VENDOR_ID, &vendor);
  304. if (vendor == 0xffff || vendor == 0x0000)
  305. continue;
  306. if (!PCI_FUNC(dev))
  307. found_multi = header_type & 0x80;
  308. debug("PCI Scan: Found Bus %d, Device %d, Function %d\n",
  309. PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
  310. pci_hose_read_config_word(hose, dev, PCI_DEVICE_ID, &device);
  311. pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
  312. #ifdef CONFIG_PCI_FIXUP_DEV
  313. board_pci_fixup_dev(hose, dev, vendor, device, class);
  314. #endif
  315. #ifdef CONFIG_PCI_SCAN_SHOW
  316. indent++;
  317. /* Print leading space, including bus indentation */
  318. printf("%*c", indent + 1, ' ');
  319. if (pci_print_dev(hose, dev)) {
  320. printf("%02x:%02x.%-*x - %04x:%04x - %s\n",
  321. PCI_BUS(dev), PCI_DEV(dev), 6 - indent, PCI_FUNC(dev),
  322. vendor, device, pci_class_str(class >> 8));
  323. }
  324. #endif
  325. #ifdef CONFIG_PCI_PNP
  326. sub_bus = max((unsigned int)pciauto_config_device(hose, dev),
  327. sub_bus);
  328. #else
  329. cfg = pci_find_config(hose, class, vendor, device,
  330. PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
  331. if (cfg) {
  332. cfg->config_device(hose, dev, cfg);
  333. sub_bus = max(sub_bus,
  334. (unsigned int)hose->current_busno);
  335. }
  336. #endif
  337. #ifdef CONFIG_PCI_SCAN_SHOW
  338. indent--;
  339. #endif
  340. if (hose->fixup_irq)
  341. hose->fixup_irq(hose, dev);
  342. }
  343. return sub_bus;
  344. }
  345. int pci_hose_scan(struct pci_controller *hose)
  346. {
  347. #if defined(CONFIG_PCI_BOOTDELAY)
  348. char *s;
  349. int i;
  350. if (!gd->pcidelay_done) {
  351. /* wait "pcidelay" ms (if defined)... */
  352. s = getenv("pcidelay");
  353. if (s) {
  354. int val = simple_strtoul(s, NULL, 10);
  355. for (i = 0; i < val; i++)
  356. udelay(1000);
  357. }
  358. gd->pcidelay_done = 1;
  359. }
  360. #endif /* CONFIG_PCI_BOOTDELAY */
  361. #ifdef CONFIG_PCI_SCAN_SHOW
  362. puts("PCI:\n");
  363. #endif
  364. /*
  365. * Start scan at current_busno.
  366. * PCIe will start scan at first_busno+1.
  367. */
  368. /* For legacy support, ensure current >= first */
  369. if (hose->first_busno > hose->current_busno)
  370. hose->current_busno = hose->first_busno;
  371. #ifdef CONFIG_PCI_PNP
  372. pciauto_config_init(hose);
  373. #endif
  374. return pci_hose_scan_bus(hose, hose->current_busno);
  375. }
  376. void pci_init(void)
  377. {
  378. hose_head = NULL;
  379. /* now call board specific pci_init()... */
  380. pci_init_board();
  381. }
  382. /* Returns the address of the requested capability structure within the
  383. * device's PCI configuration space or 0 in case the device does not
  384. * support it.
  385. * */
  386. int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev,
  387. int cap)
  388. {
  389. int pos;
  390. u8 hdr_type;
  391. pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &hdr_type);
  392. pos = pci_hose_find_cap_start(hose, dev, hdr_type & 0x7F);
  393. if (pos)
  394. pos = pci_find_cap(hose, dev, pos, cap);
  395. return pos;
  396. }
  397. /* Find the header pointer to the Capabilities*/
  398. int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev,
  399. u8 hdr_type)
  400. {
  401. u16 status;
  402. pci_hose_read_config_word(hose, dev, PCI_STATUS, &status);
  403. if (!(status & PCI_STATUS_CAP_LIST))
  404. return 0;
  405. switch (hdr_type) {
  406. case PCI_HEADER_TYPE_NORMAL:
  407. case PCI_HEADER_TYPE_BRIDGE:
  408. return PCI_CAPABILITY_LIST;
  409. case PCI_HEADER_TYPE_CARDBUS:
  410. return PCI_CB_CAPABILITY_LIST;
  411. default:
  412. return 0;
  413. }
  414. }
  415. int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos, int cap)
  416. {
  417. int ttl = PCI_FIND_CAP_TTL;
  418. u8 id;
  419. u8 next_pos;
  420. while (ttl--) {
  421. pci_hose_read_config_byte(hose, dev, pos, &next_pos);
  422. if (next_pos < CAP_START_POS)
  423. break;
  424. next_pos &= ~3;
  425. pos = (int) next_pos;
  426. pci_hose_read_config_byte(hose, dev,
  427. pos + PCI_CAP_LIST_ID, &id);
  428. if (id == 0xff)
  429. break;
  430. if (id == cap)
  431. return pos;
  432. pos += PCI_CAP_LIST_NEXT;
  433. }
  434. return 0;
  435. }
  436. /**
  437. * pci_find_next_ext_capability - Find an extended capability
  438. *
  439. * Returns the address of the next matching extended capability structure
  440. * within the device's PCI configuration space or 0 if the device does
  441. * not support it. Some capabilities can occur several times, e.g., the
  442. * vendor-specific capability, and this provides a way to find them all.
  443. */
  444. int pci_find_next_ext_capability(struct pci_controller *hose, pci_dev_t dev,
  445. int start, int cap)
  446. {
  447. u32 header;
  448. int ttl, pos = PCI_CFG_SPACE_SIZE;
  449. /* minimum 8 bytes per capability */
  450. ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
  451. if (start)
  452. pos = start;
  453. pci_hose_read_config_dword(hose, dev, pos, &header);
  454. if (header == 0xffffffff || header == 0)
  455. return 0;
  456. while (ttl-- > 0) {
  457. if (PCI_EXT_CAP_ID(header) == cap && pos != start)
  458. return pos;
  459. pos = PCI_EXT_CAP_NEXT(header);
  460. if (pos < PCI_CFG_SPACE_SIZE)
  461. break;
  462. pci_hose_read_config_dword(hose, dev, pos, &header);
  463. if (header == 0xffffffff || header == 0)
  464. break;
  465. }
  466. return 0;
  467. }
  468. /**
  469. * pci_hose_find_ext_capability - Find an extended capability
  470. *
  471. * Returns the address of the requested extended capability structure
  472. * within the device's PCI configuration space or 0 if the device does
  473. * not support it.
  474. */
  475. int pci_hose_find_ext_capability(struct pci_controller *hose, pci_dev_t dev,
  476. int cap)
  477. {
  478. return pci_find_next_ext_capability(hose, dev, 0, cap);
  479. }