omap24xx_i2c.c 15 KB

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  1. /*
  2. * Basic I2C functions
  3. *
  4. * Copyright (c) 2004 Texas Instruments
  5. *
  6. * This package is free software; you can redistribute it and/or
  7. * modify it under the terms of the license found in the file
  8. * named COPYING that should have accompanied this file.
  9. *
  10. * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
  11. * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
  12. * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
  13. *
  14. * Author: Jian Zhang jzhang@ti.com, Texas Instruments
  15. *
  16. * Copyright (c) 2003 Wolfgang Denk, wd@denx.de
  17. * Rewritten to fit into the current U-Boot framework
  18. *
  19. * Adapted for OMAP2420 I2C, r-woodruff2@ti.com
  20. *
  21. * Copyright (c) 2013 Lubomir Popov <lpopov@mm-sol.com>, MM Solutions
  22. * New i2c_read, i2c_write and i2c_probe functions, tested on OMAP4
  23. * (4430/60/70), OMAP5 (5430) and AM335X (3359); should work on older
  24. * OMAPs and derivatives as well. The only anticipated exception would
  25. * be the OMAP2420, which shall require driver modification.
  26. * - Rewritten i2c_read to operate correctly with all types of chips
  27. * (old function could not read consistent data from some I2C slaves).
  28. * - Optimized i2c_write.
  29. * - New i2c_probe, performs write access vs read. The old probe could
  30. * hang the system under certain conditions (e.g. unconfigured pads).
  31. * - The read/write/probe functions try to identify unconfigured bus.
  32. * - Status functions now read irqstatus_raw as per TRM guidelines
  33. * (except for OMAP243X and OMAP34XX).
  34. * - Driver now supports up to I2C5 (OMAP5).
  35. */
  36. #include <common.h>
  37. #include <asm/arch/i2c.h>
  38. #include <asm/io.h>
  39. #include "omap24xx_i2c.h"
  40. DECLARE_GLOBAL_DATA_PTR;
  41. #define I2C_TIMEOUT 1000
  42. /* Absolutely safe for status update at 100 kHz I2C: */
  43. #define I2C_WAIT 200
  44. static int wait_for_bb(void);
  45. static u16 wait_for_event(void);
  46. static void flush_fifo(void);
  47. /*
  48. * For SPL boot some boards need i2c before SDRAM is initialised so force
  49. * variables to live in SRAM
  50. */
  51. static struct i2c __attribute__((section (".data"))) *i2c_base =
  52. (struct i2c *)I2C_DEFAULT_BASE;
  53. static unsigned int __attribute__((section (".data"))) bus_initialized[I2C_BUS_MAX] =
  54. { [0 ... (I2C_BUS_MAX-1)] = 0 };
  55. static unsigned int __attribute__((section (".data"))) current_bus = 0;
  56. void i2c_init(int speed, int slaveadd)
  57. {
  58. int psc, fsscll, fssclh;
  59. int hsscll = 0, hssclh = 0;
  60. u32 scll, sclh;
  61. int timeout = I2C_TIMEOUT;
  62. /* Only handle standard, fast and high speeds */
  63. if ((speed != OMAP_I2C_STANDARD) &&
  64. (speed != OMAP_I2C_FAST_MODE) &&
  65. (speed != OMAP_I2C_HIGH_SPEED)) {
  66. printf("Error : I2C unsupported speed %d\n", speed);
  67. return;
  68. }
  69. psc = I2C_IP_CLK / I2C_INTERNAL_SAMPLING_CLK;
  70. psc -= 1;
  71. if (psc < I2C_PSC_MIN) {
  72. printf("Error : I2C unsupported prescalar %d\n", psc);
  73. return;
  74. }
  75. if (speed == OMAP_I2C_HIGH_SPEED) {
  76. /* High speed */
  77. /* For first phase of HS mode */
  78. fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK /
  79. (2 * OMAP_I2C_FAST_MODE);
  80. fsscll -= I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM;
  81. fssclh -= I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM;
  82. if (((fsscll < 0) || (fssclh < 0)) ||
  83. ((fsscll > 255) || (fssclh > 255))) {
  84. puts("Error : I2C initializing first phase clock\n");
  85. return;
  86. }
  87. /* For second phase of HS mode */
  88. hsscll = hssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
  89. hsscll -= I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM;
  90. hssclh -= I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM;
  91. if (((fsscll < 0) || (fssclh < 0)) ||
  92. ((fsscll > 255) || (fssclh > 255))) {
  93. puts("Error : I2C initializing second phase clock\n");
  94. return;
  95. }
  96. scll = (unsigned int)hsscll << 8 | (unsigned int)fsscll;
  97. sclh = (unsigned int)hssclh << 8 | (unsigned int)fssclh;
  98. } else {
  99. /* Standard and fast speed */
  100. fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
  101. fsscll -= I2C_FASTSPEED_SCLL_TRIM;
  102. fssclh -= I2C_FASTSPEED_SCLH_TRIM;
  103. if (((fsscll < 0) || (fssclh < 0)) ||
  104. ((fsscll > 255) || (fssclh > 255))) {
  105. puts("Error : I2C initializing clock\n");
  106. return;
  107. }
  108. scll = (unsigned int)fsscll;
  109. sclh = (unsigned int)fssclh;
  110. }
  111. if (readw(&i2c_base->con) & I2C_CON_EN) {
  112. writew(0, &i2c_base->con);
  113. udelay(50000);
  114. }
  115. writew(0x2, &i2c_base->sysc); /* for ES2 after soft reset */
  116. udelay(1000);
  117. writew(I2C_CON_EN, &i2c_base->con);
  118. while (!(readw(&i2c_base->syss) & I2C_SYSS_RDONE) && timeout--) {
  119. if (timeout <= 0) {
  120. puts("ERROR: Timeout in soft-reset\n");
  121. return;
  122. }
  123. udelay(1000);
  124. }
  125. writew(0, &i2c_base->con);
  126. writew(psc, &i2c_base->psc);
  127. writew(scll, &i2c_base->scll);
  128. writew(sclh, &i2c_base->sclh);
  129. /* own address */
  130. writew(slaveadd, &i2c_base->oa);
  131. writew(I2C_CON_EN, &i2c_base->con);
  132. #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
  133. /*
  134. * Have to enable interrupts for OMAP2/3, these IPs don't have
  135. * an 'irqstatus_raw' register and we shall have to poll 'stat'
  136. */
  137. writew(I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE |
  138. I2C_IE_NACK_IE | I2C_IE_AL_IE, &i2c_base->ie);
  139. #endif
  140. udelay(1000);
  141. flush_fifo();
  142. writew(0xFFFF, &i2c_base->stat);
  143. writew(0, &i2c_base->cnt);
  144. if (gd->flags & GD_FLG_RELOC)
  145. bus_initialized[current_bus] = 1;
  146. }
  147. static void flush_fifo(void)
  148. { u16 stat;
  149. /* note: if you try and read data when its not there or ready
  150. * you get a bus error
  151. */
  152. while (1) {
  153. stat = readw(&i2c_base->stat);
  154. if (stat == I2C_STAT_RRDY) {
  155. readb(&i2c_base->data);
  156. writew(I2C_STAT_RRDY, &i2c_base->stat);
  157. udelay(1000);
  158. } else
  159. break;
  160. }
  161. }
  162. /*
  163. * i2c_probe: Use write access. Allows to identify addresses that are
  164. * write-only (like the config register of dual-port EEPROMs)
  165. */
  166. int i2c_probe(uchar chip)
  167. {
  168. u16 status;
  169. int res = 1; /* default = fail */
  170. if (chip == readw(&i2c_base->oa))
  171. return res;
  172. /* Wait until bus is free */
  173. if (wait_for_bb())
  174. return res;
  175. /* No data transfer, slave addr only */
  176. writew(0, &i2c_base->cnt);
  177. /* Set slave address */
  178. writew(chip, &i2c_base->sa);
  179. /* Stop bit needed here */
  180. writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
  181. I2C_CON_STP, &i2c_base->con);
  182. status = wait_for_event();
  183. if ((status & ~I2C_STAT_XRDY) == 0 || (status & I2C_STAT_AL)) {
  184. /*
  185. * With current high-level command implementation, notifying
  186. * the user shall flood the console with 127 messages. If
  187. * silent exit is desired upon unconfigured bus, remove the
  188. * following 'if' section:
  189. */
  190. if (status == I2C_STAT_XRDY)
  191. printf("i2c_probe: pads on bus %d probably not configured (status=0x%x)\n",
  192. current_bus, status);
  193. goto pr_exit;
  194. }
  195. /* Check for ACK (!NAK) */
  196. if (!(status & I2C_STAT_NACK)) {
  197. res = 0; /* Device found */
  198. udelay(I2C_WAIT); /* Required by AM335X in SPL */
  199. /* Abort transfer (force idle state) */
  200. writew(I2C_CON_MST | I2C_CON_TRX, &i2c_base->con); /* Reset */
  201. udelay(1000);
  202. writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_TRX |
  203. I2C_CON_STP, &i2c_base->con); /* STP */
  204. }
  205. pr_exit:
  206. flush_fifo();
  207. writew(0xFFFF, &i2c_base->stat);
  208. writew(0, &i2c_base->cnt);
  209. return res;
  210. }
  211. /*
  212. * i2c_read: Function now uses a single I2C read transaction with bulk transfer
  213. * of the requested number of bytes (note that the 'i2c md' command
  214. * limits this to 16 bytes anyway). If CONFIG_I2C_REPEATED_START is
  215. * defined in the board config header, this transaction shall be with
  216. * Repeated Start (Sr) between the address and data phases; otherwise
  217. * Stop-Start (P-S) shall be used (some I2C chips do require a P-S).
  218. * The address (reg offset) may be 0, 1 or 2 bytes long.
  219. * Function now reads correctly from chips that return more than one
  220. * byte of data per addressed register (like TI temperature sensors),
  221. * or that do not need a register address at all (such as some clock
  222. * distributors).
  223. */
  224. int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
  225. {
  226. int i2c_error = 0;
  227. u16 status;
  228. if (alen < 0) {
  229. puts("I2C read: addr len < 0\n");
  230. return 1;
  231. }
  232. if (len < 0) {
  233. puts("I2C read: data len < 0\n");
  234. return 1;
  235. }
  236. if (buffer == NULL) {
  237. puts("I2C read: NULL pointer passed\n");
  238. return 1;
  239. }
  240. if (alen > 2) {
  241. printf("I2C read: addr len %d not supported\n", alen);
  242. return 1;
  243. }
  244. if (addr + len > (1 << 16)) {
  245. puts("I2C read: address out of range\n");
  246. return 1;
  247. }
  248. /* Wait until bus not busy */
  249. if (wait_for_bb())
  250. return 1;
  251. /* Zero, one or two bytes reg address (offset) */
  252. writew(alen, &i2c_base->cnt);
  253. /* Set slave address */
  254. writew(chip, &i2c_base->sa);
  255. if (alen) {
  256. /* Must write reg offset first */
  257. #ifdef CONFIG_I2C_REPEATED_START
  258. /* No stop bit, use Repeated Start (Sr) */
  259. writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT |
  260. I2C_CON_TRX, &i2c_base->con);
  261. #else
  262. /* Stop - Start (P-S) */
  263. writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP |
  264. I2C_CON_TRX, &i2c_base->con);
  265. #endif
  266. /* Send register offset */
  267. while (1) {
  268. status = wait_for_event();
  269. /* Try to identify bus that is not padconf'd for I2C */
  270. if (status == I2C_STAT_XRDY) {
  271. i2c_error = 2;
  272. printf("i2c_read (addr phase): pads on bus %d probably not configured (status=0x%x)\n",
  273. current_bus, status);
  274. goto rd_exit;
  275. }
  276. if (status == 0 || status & I2C_STAT_NACK) {
  277. i2c_error = 1;
  278. printf("i2c_read: error waiting for addr ACK (status=0x%x)\n",
  279. status);
  280. goto rd_exit;
  281. }
  282. if (alen) {
  283. if (status & I2C_STAT_XRDY) {
  284. alen--;
  285. /* Do we have to use byte access? */
  286. writeb((addr >> (8 * alen)) & 0xff,
  287. &i2c_base->data);
  288. writew(I2C_STAT_XRDY, &i2c_base->stat);
  289. }
  290. }
  291. if (status & I2C_STAT_ARDY) {
  292. writew(I2C_STAT_ARDY, &i2c_base->stat);
  293. break;
  294. }
  295. }
  296. }
  297. /* Set slave address */
  298. writew(chip, &i2c_base->sa);
  299. /* Read len bytes from slave */
  300. writew(len, &i2c_base->cnt);
  301. /* Need stop bit here */
  302. writew(I2C_CON_EN | I2C_CON_MST |
  303. I2C_CON_STT | I2C_CON_STP,
  304. &i2c_base->con);
  305. /* Receive data */
  306. while (1) {
  307. status = wait_for_event();
  308. /*
  309. * Try to identify bus that is not padconf'd for I2C. This
  310. * state could be left over from previous transactions if
  311. * the address phase is skipped due to alen=0.
  312. */
  313. if (status == I2C_STAT_XRDY) {
  314. i2c_error = 2;
  315. printf("i2c_read (data phase): pads on bus %d probably not configured (status=0x%x)\n",
  316. current_bus, status);
  317. goto rd_exit;
  318. }
  319. if (status == 0 || status & I2C_STAT_NACK) {
  320. i2c_error = 1;
  321. goto rd_exit;
  322. }
  323. if (status & I2C_STAT_RRDY) {
  324. *buffer++ = readb(&i2c_base->data);
  325. writew(I2C_STAT_RRDY, &i2c_base->stat);
  326. }
  327. if (status & I2C_STAT_ARDY) {
  328. writew(I2C_STAT_ARDY, &i2c_base->stat);
  329. break;
  330. }
  331. }
  332. rd_exit:
  333. flush_fifo();
  334. writew(0xFFFF, &i2c_base->stat);
  335. writew(0, &i2c_base->cnt);
  336. return i2c_error;
  337. }
  338. /* i2c_write: Address (reg offset) may be 0, 1 or 2 bytes long. */
  339. int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
  340. {
  341. int i;
  342. u16 status;
  343. int i2c_error = 0;
  344. if (alen < 0) {
  345. puts("I2C write: addr len < 0\n");
  346. return 1;
  347. }
  348. if (len < 0) {
  349. puts("I2C write: data len < 0\n");
  350. return 1;
  351. }
  352. if (buffer == NULL) {
  353. puts("I2C write: NULL pointer passed\n");
  354. return 1;
  355. }
  356. if (alen > 2) {
  357. printf("I2C write: addr len %d not supported\n", alen);
  358. return 1;
  359. }
  360. if (addr + len > (1 << 16)) {
  361. printf("I2C write: address 0x%x + 0x%x out of range\n",
  362. addr, len);
  363. return 1;
  364. }
  365. /* Wait until bus not busy */
  366. if (wait_for_bb())
  367. return 1;
  368. /* Start address phase - will write regoffset + len bytes data */
  369. writew(alen + len, &i2c_base->cnt);
  370. /* Set slave address */
  371. writew(chip, &i2c_base->sa);
  372. /* Stop bit needed here */
  373. writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
  374. I2C_CON_STP, &i2c_base->con);
  375. while (alen) {
  376. /* Must write reg offset (one or two bytes) */
  377. status = wait_for_event();
  378. /* Try to identify bus that is not padconf'd for I2C */
  379. if (status == I2C_STAT_XRDY) {
  380. i2c_error = 2;
  381. printf("i2c_write: pads on bus %d probably not configured (status=0x%x)\n",
  382. current_bus, status);
  383. goto wr_exit;
  384. }
  385. if (status == 0 || status & I2C_STAT_NACK) {
  386. i2c_error = 1;
  387. printf("i2c_write: error waiting for addr ACK (status=0x%x)\n",
  388. status);
  389. goto wr_exit;
  390. }
  391. if (status & I2C_STAT_XRDY) {
  392. alen--;
  393. writeb((addr >> (8 * alen)) & 0xff, &i2c_base->data);
  394. writew(I2C_STAT_XRDY, &i2c_base->stat);
  395. } else {
  396. i2c_error = 1;
  397. printf("i2c_write: bus not ready for addr Tx (status=0x%x)\n",
  398. status);
  399. goto wr_exit;
  400. }
  401. }
  402. /* Address phase is over, now write data */
  403. for (i = 0; i < len; i++) {
  404. status = wait_for_event();
  405. if (status == 0 || status & I2C_STAT_NACK) {
  406. i2c_error = 1;
  407. printf("i2c_write: error waiting for data ACK (status=0x%x)\n",
  408. status);
  409. goto wr_exit;
  410. }
  411. if (status & I2C_STAT_XRDY) {
  412. writeb(buffer[i], &i2c_base->data);
  413. writew(I2C_STAT_XRDY, &i2c_base->stat);
  414. } else {
  415. i2c_error = 1;
  416. printf("i2c_write: bus not ready for data Tx (i=%d)\n",
  417. i);
  418. goto wr_exit;
  419. }
  420. }
  421. wr_exit:
  422. flush_fifo();
  423. writew(0xFFFF, &i2c_base->stat);
  424. writew(0, &i2c_base->cnt);
  425. return i2c_error;
  426. }
  427. /*
  428. * Wait for the bus to be free by checking the Bus Busy (BB)
  429. * bit to become clear
  430. */
  431. static int wait_for_bb(void)
  432. {
  433. int timeout = I2C_TIMEOUT;
  434. u16 stat;
  435. writew(0xFFFF, &i2c_base->stat); /* clear current interrupts...*/
  436. #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
  437. while ((stat = readw(&i2c_base->stat) & I2C_STAT_BB) && timeout--) {
  438. #else
  439. /* Read RAW status */
  440. while ((stat = readw(&i2c_base->irqstatus_raw) &
  441. I2C_STAT_BB) && timeout--) {
  442. #endif
  443. writew(stat, &i2c_base->stat);
  444. udelay(I2C_WAIT);
  445. }
  446. if (timeout <= 0) {
  447. printf("Timed out in wait_for_bb: status=%04x\n",
  448. stat);
  449. return 1;
  450. }
  451. writew(0xFFFF, &i2c_base->stat); /* clear delayed stuff*/
  452. return 0;
  453. }
  454. /*
  455. * Wait for the I2C controller to complete current action
  456. * and update status
  457. */
  458. static u16 wait_for_event(void)
  459. {
  460. u16 status;
  461. int timeout = I2C_TIMEOUT;
  462. do {
  463. udelay(I2C_WAIT);
  464. #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
  465. status = readw(&i2c_base->stat);
  466. #else
  467. /* Read RAW status */
  468. status = readw(&i2c_base->irqstatus_raw);
  469. #endif
  470. } while (!(status &
  471. (I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY |
  472. I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK |
  473. I2C_STAT_AL)) && timeout--);
  474. if (timeout <= 0) {
  475. printf("Timed out in wait_for_event: status=%04x\n",
  476. status);
  477. /*
  478. * If status is still 0 here, probably the bus pads have
  479. * not been configured for I2C, and/or pull-ups are missing.
  480. */
  481. printf("Check if pads/pull-ups of bus %d are properly configured\n",
  482. current_bus);
  483. writew(0xFFFF, &i2c_base->stat);
  484. status = 0;
  485. }
  486. return status;
  487. }
  488. int i2c_set_bus_num(unsigned int bus)
  489. {
  490. if (bus >= I2C_BUS_MAX) {
  491. printf("Bad bus: %x\n", bus);
  492. return -1;
  493. }
  494. switch (bus) {
  495. default:
  496. bus = 0; /* Fall through */
  497. case 0:
  498. i2c_base = (struct i2c *)I2C_BASE1;
  499. break;
  500. case 1:
  501. i2c_base = (struct i2c *)I2C_BASE2;
  502. break;
  503. #if (I2C_BUS_MAX > 2)
  504. case 2:
  505. i2c_base = (struct i2c *)I2C_BASE3;
  506. break;
  507. #if (I2C_BUS_MAX > 3)
  508. case 3:
  509. i2c_base = (struct i2c *)I2C_BASE4;
  510. break;
  511. #if (I2C_BUS_MAX > 4)
  512. case 4:
  513. i2c_base = (struct i2c *)I2C_BASE5;
  514. break;
  515. #endif
  516. #endif
  517. #endif
  518. }
  519. current_bus = bus;
  520. if (!bus_initialized[current_bus])
  521. i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
  522. return 0;
  523. }
  524. int i2c_get_bus_num(void)
  525. {
  526. return (int) current_bus;
  527. }