ohci.h 14 KB

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  1. /*
  2. * URB OHCI HCD (Host Controller Driver) for USB.
  3. *
  4. * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
  5. * (C) Copyright 2000-2001 David Brownell <dbrownell@users.sourceforge.net>
  6. *
  7. * usb-ohci.h
  8. */
  9. /*
  10. * e.g. PCI controllers need this
  11. */
  12. #ifdef CONFIG_SYS_OHCI_SWAP_REG_ACCESS
  13. # define ohci_readl(a) __swap_32(*((volatile u32 *)(a)))
  14. # define ohci_writel(a, b) (*((volatile u32 *)(b)) = __swap_32((volatile u32)a))
  15. #else
  16. # define ohci_readl(a) (*((volatile u32 *)(a)))
  17. # define ohci_writel(a, b) (*((volatile u32 *)(b)) = ((volatile u32)a))
  18. #endif /* CONFIG_SYS_OHCI_SWAP_REG_ACCESS */
  19. /* functions for doing board or CPU specific setup/cleanup */
  20. int usb_board_stop(void);
  21. int usb_cpu_init(void);
  22. int usb_cpu_stop(void);
  23. int usb_cpu_init_fail(void);
  24. static int cc_to_error[16] = {
  25. /* mapping of the OHCI CC status to error codes */
  26. /* No Error */ 0,
  27. /* CRC Error */ USB_ST_CRC_ERR,
  28. /* Bit Stuff */ USB_ST_BIT_ERR,
  29. /* Data Togg */ USB_ST_CRC_ERR,
  30. /* Stall */ USB_ST_STALLED,
  31. /* DevNotResp */ -1,
  32. /* PIDCheck */ USB_ST_BIT_ERR,
  33. /* UnExpPID */ USB_ST_BIT_ERR,
  34. /* DataOver */ USB_ST_BUF_ERR,
  35. /* DataUnder */ USB_ST_BUF_ERR,
  36. /* reservd */ -1,
  37. /* reservd */ -1,
  38. /* BufferOver */ USB_ST_BUF_ERR,
  39. /* BuffUnder */ USB_ST_BUF_ERR,
  40. /* Not Access */ -1,
  41. /* Not Access */ -1
  42. };
  43. static const char *cc_to_string[16] = {
  44. "No Error",
  45. "CRC: Last data packet from endpoint contained a CRC error.",
  46. "BITSTUFFING: Last data packet from endpoint contained a bit " \
  47. "stuffing violation",
  48. "DATATOGGLEMISMATCH: Last packet from endpoint had data toggle PID\n" \
  49. "that did not match the expected value.",
  50. "STALL: TD was moved to the Done Queue because the endpoint returned" \
  51. " a STALL PID",
  52. "DEVICENOTRESPONDING: Device did not respond to token (IN) or did\n" \
  53. "not provide a handshake (OUT)",
  54. "PIDCHECKFAILURE: Check bits on PID from endpoint failed on data PID\n"\
  55. "(IN) or handshake (OUT)",
  56. "UNEXPECTEDPID: Receive PID was not valid when encountered or PID\n" \
  57. "value is not defined.",
  58. "DATAOVERRUN: The amount of data returned by the endpoint exceeded\n" \
  59. "either the size of the maximum data packet allowed\n" \
  60. "from the endpoint (found in MaximumPacketSize field\n" \
  61. "of ED) or the remaining buffer size.",
  62. "DATAUNDERRUN: The endpoint returned less than MaximumPacketSize\n" \
  63. "and that amount was not sufficient to fill the\n" \
  64. "specified buffer",
  65. "reserved1",
  66. "reserved2",
  67. "BUFFEROVERRUN: During an IN, HC received data from endpoint faster\n" \
  68. "than it could be written to system memory",
  69. "BUFFERUNDERRUN: During an OUT, HC could not retrieve data from\n" \
  70. "system memory fast enough to keep up with data USB " \
  71. "data rate.",
  72. "NOT ACCESSED: This code is set by software before the TD is placed" \
  73. "on a list to be processed by the HC.(1)",
  74. "NOT ACCESSED: This code is set by software before the TD is placed" \
  75. "on a list to be processed by the HC.(2)",
  76. };
  77. /* ED States */
  78. #define ED_NEW 0x00
  79. #define ED_UNLINK 0x01
  80. #define ED_OPER 0x02
  81. #define ED_DEL 0x04
  82. #define ED_URB_DEL 0x08
  83. /* usb_ohci_ed */
  84. struct ed {
  85. __u32 hwINFO;
  86. __u32 hwTailP;
  87. __u32 hwHeadP;
  88. __u32 hwNextED;
  89. struct ed *ed_prev;
  90. __u8 int_period;
  91. __u8 int_branch;
  92. __u8 int_load;
  93. __u8 int_interval;
  94. __u8 state;
  95. __u8 type;
  96. __u16 last_iso;
  97. struct ed *ed_rm_list;
  98. struct usb_device *usb_dev;
  99. void *purb;
  100. __u32 unused[2];
  101. } __attribute__((aligned(16)));
  102. typedef struct ed ed_t;
  103. /* TD info field */
  104. #define TD_CC 0xf0000000
  105. #define TD_CC_GET(td_p) ((td_p >>28) & 0x0f)
  106. #define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28)
  107. #define TD_EC 0x0C000000
  108. #define TD_T 0x03000000
  109. #define TD_T_DATA0 0x02000000
  110. #define TD_T_DATA1 0x03000000
  111. #define TD_T_TOGGLE 0x00000000
  112. #define TD_R 0x00040000
  113. #define TD_DI 0x00E00000
  114. #define TD_DI_SET(X) (((X) & 0x07)<< 21)
  115. #define TD_DP 0x00180000
  116. #define TD_DP_SETUP 0x00000000
  117. #define TD_DP_IN 0x00100000
  118. #define TD_DP_OUT 0x00080000
  119. #define TD_ISO 0x00010000
  120. #define TD_DEL 0x00020000
  121. /* CC Codes */
  122. #define TD_CC_NOERROR 0x00
  123. #define TD_CC_CRC 0x01
  124. #define TD_CC_BITSTUFFING 0x02
  125. #define TD_CC_DATATOGGLEM 0x03
  126. #define TD_CC_STALL 0x04
  127. #define TD_DEVNOTRESP 0x05
  128. #define TD_PIDCHECKFAIL 0x06
  129. #define TD_UNEXPECTEDPID 0x07
  130. #define TD_DATAOVERRUN 0x08
  131. #define TD_DATAUNDERRUN 0x09
  132. #define TD_BUFFEROVERRUN 0x0C
  133. #define TD_BUFFERUNDERRUN 0x0D
  134. #define TD_NOTACCESSED 0x0F
  135. #define MAXPSW 1
  136. struct td {
  137. __u32 hwINFO;
  138. __u32 hwCBP; /* Current Buffer Pointer */
  139. __u32 hwNextTD; /* Next TD Pointer */
  140. __u32 hwBE; /* Memory Buffer End Pointer */
  141. /* #ifndef CONFIG_MPC5200 /\* this seems wrong *\/ */
  142. __u16 hwPSW[MAXPSW];
  143. /* #endif */
  144. __u8 unused;
  145. __u8 index;
  146. struct ed *ed;
  147. struct td *next_dl_td;
  148. struct usb_device *usb_dev;
  149. int transfer_len;
  150. __u32 data;
  151. __u32 unused2[2];
  152. } __attribute__((aligned(32)));
  153. typedef struct td td_t;
  154. #define OHCI_ED_SKIP (1 << 14)
  155. /*
  156. * The HCCA (Host Controller Communications Area) is a 256 byte
  157. * structure defined in the OHCI spec. that the host controller is
  158. * told the base address of. It must be 256-byte aligned.
  159. */
  160. #define NUM_INTS 32 /* part of the OHCI standard */
  161. struct ohci_hcca {
  162. __u32 int_table[NUM_INTS]; /* Interrupt ED table */
  163. #if defined(CONFIG_MPC5200)
  164. __u16 pad1; /* set to 0 on each frame_no change */
  165. __u16 frame_no; /* current frame number */
  166. #else
  167. __u16 frame_no; /* current frame number */
  168. __u16 pad1; /* set to 0 on each frame_no change */
  169. #endif
  170. __u32 done_head; /* info returned for an interrupt */
  171. u8 reserved_for_hc[116];
  172. } __attribute__((aligned(256)));
  173. /*
  174. * Maximum number of root hub ports.
  175. */
  176. #ifndef CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS
  177. # error "CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS undefined!"
  178. #endif
  179. /*
  180. * This is the structure of the OHCI controller's memory mapped I/O
  181. * region. This is Memory Mapped I/O. You must use the ohci_readl() and
  182. * ohci_writel() macros defined in this file to access these!!
  183. */
  184. struct ohci_regs {
  185. /* control and status registers */
  186. __u32 revision;
  187. __u32 control;
  188. __u32 cmdstatus;
  189. __u32 intrstatus;
  190. __u32 intrenable;
  191. __u32 intrdisable;
  192. /* memory pointers */
  193. __u32 hcca;
  194. __u32 ed_periodcurrent;
  195. __u32 ed_controlhead;
  196. __u32 ed_controlcurrent;
  197. __u32 ed_bulkhead;
  198. __u32 ed_bulkcurrent;
  199. __u32 donehead;
  200. /* frame counters */
  201. __u32 fminterval;
  202. __u32 fmremaining;
  203. __u32 fmnumber;
  204. __u32 periodicstart;
  205. __u32 lsthresh;
  206. /* Root hub ports */
  207. struct ohci_roothub_regs {
  208. __u32 a;
  209. __u32 b;
  210. __u32 status;
  211. __u32 portstatus[CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS];
  212. } roothub;
  213. } __attribute__((aligned(32)));
  214. /* Some EHCI controls */
  215. #define EHCI_USBCMD_OFF 0x20
  216. #define EHCI_USBCMD_HCRESET (1 << 1)
  217. /* OHCI CONTROL AND STATUS REGISTER MASKS */
  218. /*
  219. * HcControl (control) register masks
  220. */
  221. #define OHCI_CTRL_CBSR (3 << 0) /* control/bulk service ratio */
  222. #define OHCI_CTRL_PLE (1 << 2) /* periodic list enable */
  223. #define OHCI_CTRL_IE (1 << 3) /* isochronous enable */
  224. #define OHCI_CTRL_CLE (1 << 4) /* control list enable */
  225. #define OHCI_CTRL_BLE (1 << 5) /* bulk list enable */
  226. #define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */
  227. #define OHCI_CTRL_IR (1 << 8) /* interrupt routing */
  228. #define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */
  229. #define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */
  230. /* pre-shifted values for HCFS */
  231. # define OHCI_USB_RESET (0 << 6)
  232. # define OHCI_USB_RESUME (1 << 6)
  233. # define OHCI_USB_OPER (2 << 6)
  234. # define OHCI_USB_SUSPEND (3 << 6)
  235. /*
  236. * HcCommandStatus (cmdstatus) register masks
  237. */
  238. #define OHCI_HCR (1 << 0) /* host controller reset */
  239. #define OHCI_CLF (1 << 1) /* control list filled */
  240. #define OHCI_BLF (1 << 2) /* bulk list filled */
  241. #define OHCI_OCR (1 << 3) /* ownership change request */
  242. #define OHCI_SOC (3 << 16) /* scheduling overrun count */
  243. /*
  244. * masks used with interrupt registers:
  245. * HcInterruptStatus (intrstatus)
  246. * HcInterruptEnable (intrenable)
  247. * HcInterruptDisable (intrdisable)
  248. */
  249. #define OHCI_INTR_SO (1 << 0) /* scheduling overrun */
  250. #define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */
  251. #define OHCI_INTR_SF (1 << 2) /* start frame */
  252. #define OHCI_INTR_RD (1 << 3) /* resume detect */
  253. #define OHCI_INTR_UE (1 << 4) /* unrecoverable error */
  254. #define OHCI_INTR_FNO (1 << 5) /* frame number overflow */
  255. #define OHCI_INTR_RHSC (1 << 6) /* root hub status change */
  256. #define OHCI_INTR_OC (1 << 30) /* ownership change */
  257. #define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */
  258. /* Virtual Root HUB */
  259. struct virt_root_hub {
  260. int devnum; /* Address of Root Hub endpoint */
  261. void *dev; /* was urb */
  262. void *int_addr;
  263. int send;
  264. int interval;
  265. };
  266. /* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */
  267. /* destination of request */
  268. #define RH_INTERFACE 0x01
  269. #define RH_ENDPOINT 0x02
  270. #define RH_OTHER 0x03
  271. #define RH_CLASS 0x20
  272. #define RH_VENDOR 0x40
  273. /* Requests: bRequest << 8 | bmRequestType */
  274. #define RH_GET_STATUS 0x0080
  275. #define RH_CLEAR_FEATURE 0x0100
  276. #define RH_SET_FEATURE 0x0300
  277. #define RH_SET_ADDRESS 0x0500
  278. #define RH_GET_DESCRIPTOR 0x0680
  279. #define RH_SET_DESCRIPTOR 0x0700
  280. #define RH_GET_CONFIGURATION 0x0880
  281. #define RH_SET_CONFIGURATION 0x0900
  282. #define RH_GET_STATE 0x0280
  283. #define RH_GET_INTERFACE 0x0A80
  284. #define RH_SET_INTERFACE 0x0B00
  285. #define RH_SYNC_FRAME 0x0C80
  286. /* Our Vendor Specific Request */
  287. #define RH_SET_EP 0x2000
  288. /* Hub port features */
  289. #define RH_PORT_CONNECTION 0x00
  290. #define RH_PORT_ENABLE 0x01
  291. #define RH_PORT_SUSPEND 0x02
  292. #define RH_PORT_OVER_CURRENT 0x03
  293. #define RH_PORT_RESET 0x04
  294. #define RH_PORT_POWER 0x08
  295. #define RH_PORT_LOW_SPEED 0x09
  296. #define RH_C_PORT_CONNECTION 0x10
  297. #define RH_C_PORT_ENABLE 0x11
  298. #define RH_C_PORT_SUSPEND 0x12
  299. #define RH_C_PORT_OVER_CURRENT 0x13
  300. #define RH_C_PORT_RESET 0x14
  301. /* Hub features */
  302. #define RH_C_HUB_LOCAL_POWER 0x00
  303. #define RH_C_HUB_OVER_CURRENT 0x01
  304. #define RH_DEVICE_REMOTE_WAKEUP 0x00
  305. #define RH_ENDPOINT_STALL 0x01
  306. #define RH_ACK 0x01
  307. #define RH_REQ_ERR -1
  308. #define RH_NACK 0x00
  309. /* OHCI ROOT HUB REGISTER MASKS */
  310. /* roothub.portstatus [i] bits */
  311. #define RH_PS_CCS 0x00000001 /* current connect status */
  312. #define RH_PS_PES 0x00000002 /* port enable status*/
  313. #define RH_PS_PSS 0x00000004 /* port suspend status */
  314. #define RH_PS_POCI 0x00000008 /* port over current indicator */
  315. #define RH_PS_PRS 0x00000010 /* port reset status */
  316. #define RH_PS_PPS 0x00000100 /* port power status */
  317. #define RH_PS_LSDA 0x00000200 /* low speed device attached */
  318. #define RH_PS_CSC 0x00010000 /* connect status change */
  319. #define RH_PS_PESC 0x00020000 /* port enable status change */
  320. #define RH_PS_PSSC 0x00040000 /* port suspend status change */
  321. #define RH_PS_OCIC 0x00080000 /* over current indicator change */
  322. #define RH_PS_PRSC 0x00100000 /* port reset status change */
  323. /* roothub.status bits */
  324. #define RH_HS_LPS 0x00000001 /* local power status */
  325. #define RH_HS_OCI 0x00000002 /* over current indicator */
  326. #define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */
  327. #define RH_HS_LPSC 0x00010000 /* local power status change */
  328. #define RH_HS_OCIC 0x00020000 /* over current indicator change */
  329. #define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */
  330. /* roothub.b masks */
  331. #define RH_B_DR 0x0000ffff /* device removable flags */
  332. #define RH_B_PPCM 0xffff0000 /* port power control mask */
  333. /* roothub.a masks */
  334. #define RH_A_NDP (0xff << 0) /* number of downstream ports */
  335. #define RH_A_PSM (1 << 8) /* power switching mode */
  336. #define RH_A_NPS (1 << 9) /* no power switching */
  337. #define RH_A_DT (1 << 10) /* device type (mbz) */
  338. #define RH_A_OCPM (1 << 11) /* over current protection mode */
  339. #define RH_A_NOCP (1 << 12) /* no over current protection */
  340. #define RH_A_POTPGT (0xff << 24) /* power on to power good time */
  341. /* urb */
  342. #define N_URB_TD 48
  343. typedef struct
  344. {
  345. ed_t *ed;
  346. __u16 length; /* number of tds associated with this request */
  347. __u16 td_cnt; /* number of tds already serviced */
  348. struct usb_device *dev;
  349. int state;
  350. unsigned long pipe;
  351. void *transfer_buffer;
  352. int transfer_buffer_length;
  353. int interval;
  354. int actual_length;
  355. int finished;
  356. td_t *td[N_URB_TD]; /* list pointer to all corresponding TDs associated with this request */
  357. } urb_priv_t;
  358. #define URB_DEL 1
  359. /*
  360. * This is the full ohci controller description
  361. *
  362. * Note how the "proper" USB information is just
  363. * a subset of what the full implementation needs. (Linus)
  364. */
  365. typedef struct ohci {
  366. struct ohci_hcca *hcca; /* hcca */
  367. /*dma_addr_t hcca_dma;*/
  368. int irq;
  369. int disabled; /* e.g. got a UE, we're hung */
  370. int sleeping;
  371. unsigned long flags; /* for HC bugs */
  372. struct ohci_regs *regs; /* OHCI controller's memory */
  373. int ohci_int_load[32]; /* load of the 32 Interrupt Chains (for load balancing)*/
  374. ed_t *ed_rm_list[2]; /* lists of all endpoints to be removed */
  375. ed_t *ed_bulktail; /* last endpoint of bulk list */
  376. ed_t *ed_controltail; /* last endpoint of control list */
  377. int intrstatus;
  378. __u32 hc_control; /* copy of the hc control reg */
  379. struct usb_device *dev[32];
  380. struct virt_root_hub rh;
  381. const char *slot_name;
  382. } ohci_t;
  383. #define NUM_EDS 8 /* num of preallocated endpoint descriptors */
  384. struct ohci_device {
  385. ed_t ed[NUM_EDS];
  386. int ed_cnt;
  387. };
  388. /* hcd */
  389. /* endpoint */
  390. static int ep_link(ohci_t * ohci, ed_t * ed);
  391. static int ep_unlink(ohci_t * ohci, ed_t * ed);
  392. static ed_t * ep_add_ed(struct usb_device * usb_dev, unsigned long pipe,
  393. int interval, int load);
  394. /*-------------------------------------------------------------------------*/
  395. /* we need more TDs than EDs */
  396. #define NUM_TD 64
  397. /* +1 so we can align the storage */
  398. td_t gtd[NUM_TD+1];
  399. /* pointers to aligned storage */
  400. td_t *ptd;
  401. /* TDs ... */
  402. static inline struct td *
  403. td_alloc (struct usb_device *usb_dev)
  404. {
  405. int i;
  406. struct td *td;
  407. td = NULL;
  408. for (i = 0; i < NUM_TD; i++)
  409. {
  410. if (ptd[i].usb_dev == NULL)
  411. {
  412. td = &ptd[i];
  413. td->usb_dev = usb_dev;
  414. break;
  415. }
  416. }
  417. return td;
  418. }
  419. static inline void
  420. ed_free (struct ed *ed)
  421. {
  422. ed->usb_dev = NULL;
  423. }