cpu.c 1.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2016 - 2018 Xilinx, Inc.
  4. * Michal Simek <michal.simek@xilinx.com>
  5. */
  6. #include <common.h>
  7. #include <asm/armv8/mmu.h>
  8. #include <asm/io.h>
  9. static struct mm_region versal_mem_map[] = {
  10. {
  11. .virt = 0x0UL,
  12. .phys = 0x0UL,
  13. .size = 0x80000000UL,
  14. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  15. PTE_BLOCK_INNER_SHARE
  16. }, {
  17. .virt = 0x80000000UL,
  18. .phys = 0x80000000UL,
  19. .size = 0x70000000UL,
  20. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  21. PTE_BLOCK_NON_SHARE |
  22. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  23. }, {
  24. .virt = 0xf0000000UL,
  25. .phys = 0xf0000000UL,
  26. .size = 0x0fe00000UL,
  27. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  28. PTE_BLOCK_NON_SHARE |
  29. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  30. }, {
  31. .virt = 0xffe00000UL,
  32. .phys = 0xffe00000UL,
  33. .size = 0x00200000UL,
  34. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  35. PTE_BLOCK_INNER_SHARE
  36. }, {
  37. .virt = 0x400000000UL,
  38. .phys = 0x400000000UL,
  39. .size = 0x200000000UL,
  40. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  41. PTE_BLOCK_NON_SHARE |
  42. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  43. }, {
  44. .virt = 0x600000000UL,
  45. .phys = 0x600000000UL,
  46. .size = 0x800000000UL,
  47. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  48. PTE_BLOCK_INNER_SHARE
  49. }, {
  50. .virt = 0xe00000000UL,
  51. .phys = 0xe00000000UL,
  52. .size = 0xf200000000UL,
  53. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  54. PTE_BLOCK_NON_SHARE |
  55. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  56. }, {
  57. /* List terminator */
  58. 0,
  59. }
  60. };
  61. struct mm_region *mem_map = versal_mem_map;
  62. u64 get_page_table_size(void)
  63. {
  64. return 0x14000;
  65. }