immap_lsch3.h 5.9 KB

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  1. /*
  2. * LayerScape Internal Memory Map
  3. *
  4. * Copyright 2014 Freescale Semiconductor, Inc.
  5. *
  6. * SPDX-License-Identifier: GPL-2.0+
  7. */
  8. #ifndef __ARCH_FSL_LSCH3_IMMAP_H
  9. #define __ARCH_FSL_LSCH3_IMMAP_H_
  10. /* This is chassis generation 3 */
  11. struct sys_info {
  12. unsigned long freq_processor[CONFIG_MAX_CPUS];
  13. unsigned long freq_systembus;
  14. unsigned long freq_ddrbus;
  15. unsigned long freq_ddrbus2;
  16. unsigned long freq_localbus;
  17. unsigned long freq_qe;
  18. #ifdef CONFIG_SYS_DPAA_FMAN
  19. unsigned long freq_fman[CONFIG_SYS_NUM_FMAN];
  20. #endif
  21. #ifdef CONFIG_SYS_DPAA_QBMAN
  22. unsigned long freq_qman;
  23. #endif
  24. #ifdef CONFIG_SYS_DPAA_PME
  25. unsigned long freq_pme;
  26. #endif
  27. };
  28. /* Global Utilities Block */
  29. struct ccsr_gur {
  30. u32 porsr1; /* POR status 1 */
  31. u32 porsr2; /* POR status 2 */
  32. u8 res_008[0x20-0x8];
  33. u32 gpporcr1; /* General-purpose POR configuration */
  34. u32 gpporcr2; /* General-purpose POR configuration 2 */
  35. u32 dcfg_fusesr; /* Fuse status register */
  36. u32 gpporcr3;
  37. u32 gpporcr4;
  38. u8 res_034[0x70-0x34];
  39. u32 devdisr; /* Device disable control */
  40. u32 devdisr2; /* Device disable control 2 */
  41. u32 devdisr3; /* Device disable control 3 */
  42. u32 devdisr4; /* Device disable control 4 */
  43. u32 devdisr5; /* Device disable control 5 */
  44. u32 devdisr6; /* Device disable control 6 */
  45. u32 devdisr7; /* Device disable control 7 */
  46. #define FSL_CHASSIS3_DEVDISR2_DPMAC1 0x00000001
  47. #define FSL_CHASSIS3_DEVDISR2_DPMAC2 0x00000002
  48. #define FSL_CHASSIS3_DEVDISR2_DPMAC3 0x00000004
  49. #define FSL_CHASSIS3_DEVDISR2_DPMAC4 0x00000008
  50. #define FSL_CHASSIS3_DEVDISR2_DPMAC5 0x00000010
  51. #define FSL_CHASSIS3_DEVDISR2_DPMAC6 0x00000020
  52. #define FSL_CHASSIS3_DEVDISR2_DPMAC7 0x00000040
  53. #define FSL_CHASSIS3_DEVDISR2_DPMAC8 0x00000080
  54. #define FSL_CHASSIS3_DEVDISR2_DPMAC9 0x00000100
  55. #define FSL_CHASSIS3_DEVDISR2_DPMAC10 0x00000200
  56. #define FSL_CHASSIS3_DEVDISR2_DPMAC11 0x00000400
  57. #define FSL_CHASSIS3_DEVDISR2_DPMAC12 0x00000800
  58. #define FSL_CHASSIS3_DEVDISR2_DPMAC13 0x00001000
  59. #define FSL_CHASSIS3_DEVDISR2_DPMAC14 0x00002000
  60. #define FSL_CHASSIS3_DEVDISR2_DPMAC15 0x00004000
  61. #define FSL_CHASSIS3_DEVDISR2_DPMAC16 0x00008000
  62. #define FSL_CHASSIS3_DEVDISR2_DPMAC17 0x00010000
  63. #define FSL_CHASSIS3_DEVDISR2_DPMAC18 0x00020000
  64. #define FSL_CHASSIS3_DEVDISR2_DPMAC19 0x00040000
  65. #define FSL_CHASSIS3_DEVDISR2_DPMAC20 0x00080000
  66. #define FSL_CHASSIS3_DEVDISR2_DPMAC21 0x00100000
  67. #define FSL_CHASSIS3_DEVDISR2_DPMAC22 0x00200000
  68. #define FSL_CHASSIS3_DEVDISR2_DPMAC23 0x00400000
  69. #define FSL_CHASSIS3_DEVDISR2_DPMAC24 0x00800000
  70. u8 res_08c[0x90-0x8c];
  71. u32 coredisru; /* uppper portion for support of 64 cores */
  72. u32 coredisrl; /* lower portion for support of 64 cores */
  73. u8 res_098[0xa0-0x98];
  74. u32 pvr; /* Processor version */
  75. u32 svr; /* System version */
  76. u32 mvr; /* Manufacturing version */
  77. u8 res_0ac[0x100-0xac];
  78. u32 rcwsr[32]; /* Reset control word status */
  79. #define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT 2
  80. #define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK 0x1f
  81. #define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT 10
  82. #define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK 0x3f
  83. #define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT 18
  84. #define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK 0x3f
  85. #define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK 0x00FF0000
  86. #define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT 16
  87. #define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK 0xFF000000
  88. #define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT 24
  89. u8 res_180[0x200-0x180];
  90. u32 scratchrw[32]; /* Scratch Read/Write */
  91. u8 res_280[0x300-0x280];
  92. u32 scratchw1r[4]; /* Scratch Read (Write once) */
  93. u8 res_310[0x400-0x310];
  94. u32 bootlocptrl; /* Boot location pointer low-order addr */
  95. u32 bootlocptrh; /* Boot location pointer high-order addr */
  96. u8 res_408[0x500-0x408];
  97. u8 res_500[0x740-0x500]; /* add more registers when needed */
  98. u32 tp_ityp[64]; /* Topology Initiator Type Register */
  99. struct {
  100. u32 upper;
  101. u32 lower;
  102. } tp_cluster[3]; /* Core Cluster n Topology Register */
  103. u8 res_858[0x1000-0x858];
  104. };
  105. #define TP_ITYP_AV 0x00000001 /* Initiator available */
  106. #define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */
  107. #define TP_ITYP_TYPE_ARM 0x0
  108. #define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */
  109. #define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */
  110. #define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */
  111. #define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */
  112. #define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */
  113. #define TY_ITYP_VER_A7 0x1
  114. #define TY_ITYP_VER_A53 0x2
  115. #define TY_ITYP_VER_A57 0x3
  116. #define TP_CLUSTER_EOC 0x80000000 /* end of clusters */
  117. #define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */
  118. #define TP_INIT_PER_CLUSTER 4
  119. struct ccsr_clk_cluster_group {
  120. struct {
  121. u8 res_00[0x10];
  122. u32 csr;
  123. u8 res_14[0x20-0x14];
  124. } hwncsr[3];
  125. u8 res_60[0x80-0x60];
  126. struct {
  127. u32 gsr;
  128. u8 res_84[0xa0-0x84];
  129. } pllngsr[3];
  130. u8 res_e0[0x100-0xe0];
  131. };
  132. struct ccsr_clk_ctrl {
  133. struct {
  134. u32 csr; /* core cluster n clock control status */
  135. u8 res_04[0x20-0x04];
  136. } clkcncsr[8];
  137. };
  138. struct ccsr_reset {
  139. u32 rstcr; /* 0x000 */
  140. u32 rstcrsp; /* 0x004 */
  141. u8 res_008[0x10-0x08]; /* 0x008 */
  142. u32 rstrqmr1; /* 0x010 */
  143. u32 rstrqmr2; /* 0x014 */
  144. u32 rstrqsr1; /* 0x018 */
  145. u32 rstrqsr2; /* 0x01c */
  146. u32 rstrqwdtmrl; /* 0x020 */
  147. u32 rstrqwdtmru; /* 0x024 */
  148. u8 res_028[0x30-0x28]; /* 0x028 */
  149. u32 rstrqwdtsrl; /* 0x030 */
  150. u32 rstrqwdtsru; /* 0x034 */
  151. u8 res_038[0x60-0x38]; /* 0x038 */
  152. u32 brrl; /* 0x060 */
  153. u32 brru; /* 0x064 */
  154. u8 res_068[0x80-0x68]; /* 0x068 */
  155. u32 pirset; /* 0x080 */
  156. u32 pirclr; /* 0x084 */
  157. u8 res_088[0x90-0x88]; /* 0x088 */
  158. u32 brcorenbr; /* 0x090 */
  159. u8 res_094[0x100-0x94]; /* 0x094 */
  160. u32 rcw_reqr; /* 0x100 */
  161. u32 rcw_completion; /* 0x104 */
  162. u8 res_108[0x110-0x108]; /* 0x108 */
  163. u32 pbi_reqr; /* 0x110 */
  164. u32 pbi_completion; /* 0x114 */
  165. u8 res_118[0xa00-0x118]; /* 0x118 */
  166. u32 qmbm_warmrst; /* 0xa00 */
  167. u32 soc_warmrst; /* 0xa04 */
  168. u8 res_a08[0xbf8-0xa08]; /* 0xa08 */
  169. u32 ip_rev1; /* 0xbf8 */
  170. u32 ip_rev2; /* 0xbfc */
  171. };
  172. #endif /* __ARCH_FSL_LSCH3_IMMAP_H */