clock.c 5.4 KB

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  1. /*
  2. * (C) Copyright 2015
  3. * Kamil Lulko, <rev13@wp.pl>
  4. *
  5. * (C) Copyright 2014
  6. * STMicroelectronics
  7. *
  8. * SPDX-License-Identifier: GPL-2.0+
  9. */
  10. #include <common.h>
  11. #include <asm/io.h>
  12. #include <asm/arch/stm32.h>
  13. #define RCC_CR_HSION (1 << 0)
  14. #define RCC_CR_HSEON (1 << 16)
  15. #define RCC_CR_HSERDY (1 << 17)
  16. #define RCC_CR_HSEBYP (1 << 18)
  17. #define RCC_CR_CSSON (1 << 19)
  18. #define RCC_CR_PLLON (1 << 24)
  19. #define RCC_CR_PLLRDY (1 << 25)
  20. #define RCC_PLLCFGR_PLLM_MASK 0x3F
  21. #define RCC_PLLCFGR_PLLN_MASK 0x7FC0
  22. #define RCC_PLLCFGR_PLLP_MASK 0x30000
  23. #define RCC_PLLCFGR_PLLQ_MASK 0xF000000
  24. #define RCC_PLLCFGR_PLLSRC (1 << 22)
  25. #define RCC_PLLCFGR_PLLN_SHIFT 6
  26. #define RCC_PLLCFGR_PLLP_SHIFT 16
  27. #define RCC_PLLCFGR_PLLQ_SHIFT 24
  28. #define RCC_CFGR_AHB_PSC_MASK 0xF0
  29. #define RCC_CFGR_APB1_PSC_MASK 0x1C00
  30. #define RCC_CFGR_APB2_PSC_MASK 0xE000
  31. #define RCC_CFGR_SW0 (1 << 0)
  32. #define RCC_CFGR_SW1 (1 << 1)
  33. #define RCC_CFGR_SW_MASK 0x3
  34. #define RCC_CFGR_SW_HSI 0
  35. #define RCC_CFGR_SW_HSE RCC_CFGR_SW0
  36. #define RCC_CFGR_SW_PLL RCC_CFGR_SW1
  37. #define RCC_CFGR_SWS0 (1 << 2)
  38. #define RCC_CFGR_SWS1 (1 << 3)
  39. #define RCC_CFGR_SWS_MASK 0xC
  40. #define RCC_CFGR_SWS_HSI 0
  41. #define RCC_CFGR_SWS_HSE RCC_CFGR_SWS0
  42. #define RCC_CFGR_SWS_PLL RCC_CFGR_SWS1
  43. #define RCC_CFGR_HPRE_SHIFT 4
  44. #define RCC_CFGR_PPRE1_SHIFT 10
  45. #define RCC_CFGR_PPRE2_SHIFT 13
  46. #define RCC_APB1ENR_PWREN (1 << 28)
  47. #define PWR_CR_VOS0 (1 << 14)
  48. #define PWR_CR_VOS1 (1 << 15)
  49. #define PWR_CR_VOS_MASK 0xC000
  50. #define PWR_CR_VOS_SCALE_MODE_1 (PWR_CR_VOS0 | PWR_CR_VOS1)
  51. #define PWR_CR_VOS_SCALE_MODE_2 (PWR_CR_VOS1)
  52. #define PWR_CR_VOS_SCALE_MODE_3 (PWR_CR_VOS0)
  53. #define FLASH_ACR_WS(n) n
  54. #define FLASH_ACR_PRFTEN (1 << 8)
  55. #define FLASH_ACR_ICEN (1 << 9)
  56. #define FLASH_ACR_DCEN (1 << 10)
  57. struct pll_psc {
  58. u8 pll_m;
  59. u16 pll_n;
  60. u8 pll_p;
  61. u8 pll_q;
  62. u8 ahb_psc;
  63. u8 apb1_psc;
  64. u8 apb2_psc;
  65. };
  66. #define AHB_PSC_1 0
  67. #define AHB_PSC_2 0x8
  68. #define AHB_PSC_4 0x9
  69. #define AHB_PSC_8 0xA
  70. #define AHB_PSC_16 0xB
  71. #define AHB_PSC_64 0xC
  72. #define AHB_PSC_128 0xD
  73. #define AHB_PSC_256 0xE
  74. #define AHB_PSC_512 0xF
  75. #define APB_PSC_1 0
  76. #define APB_PSC_2 0x4
  77. #define APB_PSC_4 0x5
  78. #define APB_PSC_8 0x6
  79. #define APB_PSC_16 0x7
  80. #if !defined(CONFIG_STM32_HSE_HZ)
  81. #error "CONFIG_STM32_HSE_HZ not defined!"
  82. #else
  83. #if (CONFIG_STM32_HSE_HZ == 8000000)
  84. struct pll_psc pll_psc_168 = {
  85. .pll_m = 8,
  86. .pll_n = 336,
  87. .pll_p = 2,
  88. .pll_q = 7,
  89. .ahb_psc = AHB_PSC_1,
  90. .apb1_psc = APB_PSC_4,
  91. .apb2_psc = APB_PSC_2
  92. };
  93. #else
  94. #error "No PLL/Prescaler configuration for given CONFIG_STM32_HSE_HZ exists"
  95. #endif
  96. #endif
  97. int configure_clocks(void)
  98. {
  99. /* Reset RCC configuration */
  100. setbits_le32(&STM32_RCC->cr, RCC_CR_HSION);
  101. writel(0, &STM32_RCC->cfgr); /* Reset CFGR */
  102. clrbits_le32(&STM32_RCC->cr, (RCC_CR_HSEON | RCC_CR_CSSON
  103. | RCC_CR_PLLON));
  104. writel(0x24003010, &STM32_RCC->pllcfgr); /* Reset value from RM */
  105. clrbits_le32(&STM32_RCC->cr, RCC_CR_HSEBYP);
  106. writel(0, &STM32_RCC->cir); /* Disable all interrupts */
  107. /* Configure for HSE+PLL operation */
  108. setbits_le32(&STM32_RCC->cr, RCC_CR_HSEON);
  109. while (!(readl(&STM32_RCC->cr) & RCC_CR_HSERDY))
  110. ;
  111. /* Enable high performance mode, System frequency up to 168 MHz */
  112. setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_PWREN);
  113. writel(PWR_CR_VOS_SCALE_MODE_1, &STM32_PWR->cr);
  114. setbits_le32(&STM32_RCC->cfgr, ((
  115. pll_psc_168.ahb_psc << RCC_CFGR_HPRE_SHIFT)
  116. | (pll_psc_168.apb1_psc << RCC_CFGR_PPRE1_SHIFT)
  117. | (pll_psc_168.apb2_psc << RCC_CFGR_PPRE2_SHIFT)));
  118. writel(pll_psc_168.pll_m
  119. | (pll_psc_168.pll_n << RCC_PLLCFGR_PLLN_SHIFT)
  120. | (((pll_psc_168.pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT)
  121. | (pll_psc_168.pll_q << RCC_PLLCFGR_PLLQ_SHIFT),
  122. &STM32_RCC->pllcfgr);
  123. setbits_le32(&STM32_RCC->pllcfgr, RCC_PLLCFGR_PLLSRC);
  124. setbits_le32(&STM32_RCC->cr, RCC_CR_PLLON);
  125. while (!(readl(&STM32_RCC->cr) & RCC_CR_PLLRDY))
  126. ;
  127. /* 5 wait states, Prefetch enabled, D-Cache enabled, I-Cache enabled */
  128. writel(FLASH_ACR_WS(5) | FLASH_ACR_PRFTEN | FLASH_ACR_ICEN
  129. | FLASH_ACR_DCEN, &STM32_FLASH->acr);
  130. clrbits_le32(&STM32_RCC->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1));
  131. setbits_le32(&STM32_RCC->cfgr, RCC_CFGR_SW_PLL);
  132. while ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) !=
  133. RCC_CFGR_SWS_PLL)
  134. ;
  135. return 0;
  136. }
  137. unsigned long clock_get(enum clock clck)
  138. {
  139. u32 sysclk = 0;
  140. u32 shift = 0;
  141. /* Prescaler table lookups for clock computation */
  142. u8 ahb_psc_table[16] = {
  143. 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9
  144. };
  145. u8 apb_psc_table[8] = {
  146. 0, 0, 0, 0, 1, 2, 3, 4
  147. };
  148. if ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) ==
  149. RCC_CFGR_SWS_PLL) {
  150. u16 pllm, plln, pllp;
  151. pllm = (readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
  152. plln = ((readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLN_MASK)
  153. >> RCC_PLLCFGR_PLLN_SHIFT);
  154. pllp = ((((readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLP_MASK)
  155. >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1);
  156. sysclk = ((CONFIG_STM32_HSE_HZ / pllm) * plln) / pllp;
  157. }
  158. switch (clck) {
  159. case CLOCK_CORE:
  160. return sysclk;
  161. break;
  162. case CLOCK_AHB:
  163. shift = ahb_psc_table[(
  164. (readl(&STM32_RCC->cfgr) & RCC_CFGR_AHB_PSC_MASK)
  165. >> RCC_CFGR_HPRE_SHIFT)];
  166. return sysclk >>= shift;
  167. break;
  168. case CLOCK_APB1:
  169. shift = apb_psc_table[(
  170. (readl(&STM32_RCC->cfgr) & RCC_CFGR_APB1_PSC_MASK)
  171. >> RCC_CFGR_PPRE1_SHIFT)];
  172. return sysclk >>= shift;
  173. break;
  174. case CLOCK_APB2:
  175. shift = apb_psc_table[(
  176. (readl(&STM32_RCC->cfgr) & RCC_CFGR_APB2_PSC_MASK)
  177. >> RCC_CFGR_PPRE2_SHIFT)];
  178. return sysclk >>= shift;
  179. break;
  180. default:
  181. return 0;
  182. break;
  183. }
  184. }