dm355leopard.c 2.1 KB

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  1. /*
  2. * Copyright (C) 2009 Texas Instruments Incorporated
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #include <common.h>
  7. #include <nand.h>
  8. #include <asm/io.h>
  9. #include <asm/arch/hardware.h>
  10. #include <asm/arch/gpio.h>
  11. #include <asm/ti-common/davinci_nand.h>
  12. #include <asm/arch/davinci_misc.h>
  13. #include <net.h>
  14. #include <netdev.h>
  15. DECLARE_GLOBAL_DATA_PTR;
  16. int board_init(void)
  17. {
  18. struct davinci_gpio *gpio01_base =
  19. (struct davinci_gpio *)DAVINCI_GPIO_BANK01;
  20. struct davinci_gpio *gpio23_base =
  21. (struct davinci_gpio *)DAVINCI_GPIO_BANK23;
  22. struct davinci_gpio *gpio67_base =
  23. (struct davinci_gpio *)DAVINCI_GPIO_BANK67;
  24. gd->bd->bi_arch_number = MACH_TYPE_DM355_LEOPARD;
  25. gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
  26. /* GIO 9 & 10 are used for IO */
  27. writel((readl(PINMUX3) & 0XF8FFFFFF), PINMUX3);
  28. /* Interrupt set GIO 9 */
  29. writel((readl(DAVINCI_GPIO_BINTEN) | 0x1), DAVINCI_GPIO_BINTEN);
  30. /* set GIO 9 input */
  31. writel((readl(&gpio01_base->dir) | (1 << 9)), &gpio01_base->dir);
  32. /* Both edge trigger GIO 9 */
  33. writel((readl(&gpio01_base->set_rising) | (1 << 9)),
  34. &gpio01_base->set_rising);
  35. writel((readl(&gpio01_base->dir) & ~(1 << 5)), &gpio01_base->dir);
  36. /* output low */
  37. writel((readl(&gpio01_base->set_data) & ~(1 << 5)),
  38. &gpio01_base->set_data);
  39. /* set GIO 10 output */
  40. writel((readl(&gpio01_base->dir) & ~(1 << 10)), &gpio01_base->dir);
  41. /* output high */
  42. writel((readl(&gpio01_base->set_data) | (1 << 10)),
  43. &gpio01_base->set_data);
  44. /* set GIO 32 output */
  45. writel((readl(&gpio23_base->dir) & ~(1 << 0)), &gpio23_base->dir);
  46. /* output High */
  47. writel((readl(&gpio23_base->set_data) | (1 << 0)),
  48. &gpio23_base->set_data);
  49. /* Enable UART1 MUX Lines */
  50. writel((readl(PINMUX0) & ~3), PINMUX0);
  51. writel((readl(&gpio67_base->dir) & ~(1 << 6)), &gpio67_base->dir);
  52. writel((readl(&gpio67_base->set_data) | (1 << 6)),
  53. &gpio67_base->set_data);
  54. return 0;
  55. }
  56. #ifdef CONFIG_DRIVER_DM9000
  57. int board_eth_init(bd_t *bis)
  58. {
  59. return dm9000_initialize(bis);
  60. }
  61. #endif
  62. #ifdef CONFIG_NAND_DAVINCI
  63. int board_nand_init(struct nand_chip *nand)
  64. {
  65. davinci_nand_init(nand);
  66. return 0;
  67. }
  68. #endif