fsl_secure_boot.h 4.3 KB

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  1. /*
  2. * Copyright 2010-2011 Freescale Semiconductor, Inc.
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #ifndef __FSL_SECURE_BOOT_H
  7. #define __FSL_SECURE_BOOT_H
  8. #include <asm/config_mpc85xx.h>
  9. #ifdef CONFIG_SECURE_BOOT
  10. #ifndef CONFIG_FIT_SIGNATURE
  11. #define CONFIG_CHAIN_OF_TRUST
  12. #endif
  13. #if defined(CONFIG_FSL_CORENET)
  14. #define CONFIG_SYS_PBI_FLASH_BASE 0xc0000000
  15. #elif defined(CONFIG_TARGET_BSC9132QDS)
  16. #define CONFIG_SYS_PBI_FLASH_BASE 0xc8000000
  17. #elif defined(CONFIG_TARGET_C29XPCIE)
  18. #define CONFIG_SYS_PBI_FLASH_BASE 0xcc000000
  19. #else
  20. #define CONFIG_SYS_PBI_FLASH_BASE 0xce000000
  21. #endif
  22. #define CONFIG_SYS_PBI_FLASH_WINDOW 0xcff80000
  23. #if defined(CONFIG_TARGET_B4860QDS) || \
  24. defined(CONFIG_TARGET_B4420QDS) || \
  25. defined(CONFIG_T4240QDS) || \
  26. defined(CONFIG_T2080QDS) || \
  27. defined(CONFIG_T2080RDB) || \
  28. defined(CONFIG_T1040QDS) || \
  29. defined(CONFIG_T104xD4QDS) || \
  30. defined(CONFIG_T104xRDB) || \
  31. defined(CONFIG_T104xD4RDB) || \
  32. defined(CONFIG_ARCH_T1023) || \
  33. defined(CONFIG_ARCH_T1024)
  34. #ifndef CONFIG_SYS_RAMBOOT
  35. #define CONFIG_SYS_CPC_REINIT_F
  36. #endif
  37. #define CONFIG_KEY_REVOCATION
  38. #undef CONFIG_SYS_INIT_L3_ADDR
  39. #define CONFIG_SYS_INIT_L3_ADDR 0xbff00000
  40. #endif
  41. #if defined(CONFIG_RAMBOOT_PBL)
  42. #undef CONFIG_SYS_INIT_L3_ADDR
  43. #ifdef CONFIG_SYS_INIT_L3_VADDR
  44. #define CONFIG_SYS_INIT_L3_ADDR \
  45. (CONFIG_SYS_INIT_L3_VADDR & ~0xFFF00000) | \
  46. 0xbff00000
  47. #else
  48. #define CONFIG_SYS_INIT_L3_ADDR 0xbff00000
  49. #endif
  50. #endif
  51. #if defined(CONFIG_TARGET_C29XPCIE)
  52. #define CONFIG_KEY_REVOCATION
  53. #endif
  54. #if defined(CONFIG_ARCH_P3041) || \
  55. defined(CONFIG_ARCH_P4080) || \
  56. defined(CONFIG_ARCH_P5020) || \
  57. defined(CONFIG_ARCH_P5040) || \
  58. defined(CONFIG_ARCH_P2041)
  59. #define CONFIG_FSL_TRUST_ARCH_v1
  60. #endif
  61. #if defined(CONFIG_FSL_CORENET) && !defined(CONFIG_SYS_RAMBOOT)
  62. /* The key used for verification of next level images
  63. * is picked up from an Extension Table which has
  64. * been verified by the ISBC (Internal Secure boot Code)
  65. * in boot ROM of the SoC.
  66. * The feature is only applicable in case of NOR boot and is
  67. * not applicable in case of RAMBOOT (NAND, SD, SPI).
  68. */
  69. #define CONFIG_FSL_ISBC_KEY_EXT
  70. #endif
  71. #endif /* #ifdef CONFIG_SECURE_BOOT */
  72. #ifdef CONFIG_CHAIN_OF_TRUST
  73. #ifdef CONFIG_SPL_BUILD
  74. /*
  75. * PPAACT and SPAACT table for PAMU must be placed on DDR after DDR init
  76. * due to space crunch on CPC and thus malloc will not work.
  77. */
  78. #define CONFIG_SPL_PPAACT_ADDR 0x2e000000
  79. #define CONFIG_SPL_SPAACT_ADDR 0x2f000000
  80. #define CONFIG_SPL_JR0_LIODN_S 454
  81. #define CONFIG_SPL_JR0_LIODN_NS 458
  82. /*
  83. * Define the key hash for U-Boot here if public/private key pair used to
  84. * sign U-boot are different from the SRK hash put in the fuse
  85. * Example of defining KEY_HASH is
  86. * #define CONFIG_SPL_UBOOT_KEY_HASH \
  87. * "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b"
  88. * else leave it defined as NULL
  89. */
  90. #define CONFIG_SPL_UBOOT_KEY_HASH NULL
  91. #endif /* ifdef CONFIG_SPL_BUILD */
  92. #define CONFIG_CMD_ESBC_VALIDATE
  93. #define CONFIG_CMD_BLOB
  94. #define CONFIG_FSL_SEC_MON
  95. #define CONFIG_SHA_PROG_HW_ACCEL
  96. #define CONFIG_RSA_FREESCALE_EXP
  97. #ifndef CONFIG_FSL_CAAM
  98. #define CONFIG_FSL_CAAM
  99. #endif
  100. #ifndef CONFIG_SPL_BUILD
  101. /*
  102. * fsl_setenv_chain_of_trust() must be called from
  103. * board_late_init()
  104. */
  105. #ifndef CONFIG_BOARD_LATE_INIT
  106. #define CONFIG_BOARD_LATE_INIT
  107. #endif
  108. /* If Boot Script is not on NOR and is required to be copied on RAM */
  109. #ifdef CONFIG_BOOTSCRIPT_COPY_RAM
  110. #define CONFIG_BS_HDR_ADDR_RAM 0x00010000
  111. #define CONFIG_BS_HDR_ADDR_DEVICE 0x00800000
  112. #define CONFIG_BS_HDR_SIZE 0x00002000
  113. #define CONFIG_BS_ADDR_RAM 0x00012000
  114. #define CONFIG_BS_ADDR_DEVICE 0x00802000
  115. #define CONFIG_BS_SIZE 0x00001000
  116. #define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_RAM
  117. #else
  118. /* The bootscript header address is different for B4860 because the NOR
  119. * mapping is different on B4 due to reduced NOR size.
  120. */
  121. #if defined(CONFIG_TARGET_B4860QDS) || defined(CONFIG_TARGET_B4420QDS)
  122. #define CONFIG_BOOTSCRIPT_HDR_ADDR 0xecc00000
  123. #elif defined(CONFIG_FSL_CORENET)
  124. #define CONFIG_BOOTSCRIPT_HDR_ADDR 0xe8e00000
  125. #elif defined(CONFIG_TARGET_BSC9132QDS)
  126. #define CONFIG_BOOTSCRIPT_HDR_ADDR 0x88020000
  127. #elif defined(CONFIG_TARGET_C29XPCIE)
  128. #define CONFIG_BOOTSCRIPT_HDR_ADDR 0xec020000
  129. #else
  130. #define CONFIG_BOOTSCRIPT_HDR_ADDR 0xee020000
  131. #endif
  132. #endif /* #ifdef CONFIG_BOOTSCRIPT_COPY_RAM */
  133. #include <config_fsl_chain_trust.h>
  134. #endif /* #ifndef CONFIG_SPL_BUILD */
  135. #endif /* #ifdef CONFIG_CHAIN_OF_TRUST */
  136. #endif