4xx_ibm_ddr2_autocalib.c 35 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251
  1. /*
  2. * arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c
  3. * This SPD SDRAM detection code supports AMCC PPC44x cpu's with a
  4. * DDR2 controller (non Denali Core). Those currently are:
  5. *
  6. * 405: 405EX
  7. * 440/460: 440SP/440SPe/460EX/460GT/460SX
  8. *
  9. * (C) Copyright 2008 Applied Micro Circuits Corporation
  10. * Adam Graham <agraham@amcc.com>
  11. *
  12. * (C) Copyright 2007-2008
  13. * Stefan Roese, DENX Software Engineering, sr@denx.de.
  14. *
  15. * COPYRIGHT AMCC CORPORATION 2004
  16. *
  17. * See file CREDITS for list of people who contributed to this
  18. * project.
  19. *
  20. * This program is free software; you can redistribute it and/or
  21. * modify it under the terms of the GNU General Public License as
  22. * published by the Free Software Foundation; either version 2 of
  23. * the License, or (at your option) any later version.
  24. *
  25. * This program is distributed in the hope that it will be useful,
  26. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  27. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  28. * GNU General Public License for more details.
  29. *
  30. * You should have received a copy of the GNU General Public License
  31. * along with this program; if not, write to the Free Software
  32. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  33. * MA 02111-1307 USA
  34. *
  35. */
  36. /* define DEBUG for debugging output (obviously ;-)) */
  37. #undef DEBUG
  38. #include <common.h>
  39. #include <ppc4xx.h>
  40. #include <asm/io.h>
  41. #include <asm/processor.h>
  42. #include "ecc.h"
  43. #if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
  44. /*
  45. * Only compile the DDR auto-calibration code for NOR boot and
  46. * not for NAND boot (NAND SPL and NAND U-Boot - NUB)
  47. */
  48. #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
  49. #define MAXBXCF 4
  50. #define SDRAM_RXBAS_SHIFT_1M 20
  51. #if defined(CONFIG_SYS_DECREMENT_PATTERNS)
  52. #define NUMMEMTESTS 24
  53. #else
  54. #define NUMMEMTESTS 8
  55. #endif /* CONFIG_SYS_DECREMENT_PATTERNS */
  56. #define NUMLOOPS 1 /* configure as you deem approporiate */
  57. #define NUMMEMWORDS 16
  58. #define SDRAM_RDCC_RDSS_VAL(n) SDRAM_RDCC_RDSS_DECODE(ddr_rdss_opt(n))
  59. /* Private Structure Definitions */
  60. struct autocal_regs {
  61. u32 rffd;
  62. u32 rqfd;
  63. };
  64. struct ddrautocal {
  65. u32 rffd;
  66. u32 rffd_min;
  67. u32 rffd_max;
  68. u32 rffd_size;
  69. u32 rqfd;
  70. u32 rqfd_size;
  71. u32 rdcc;
  72. u32 flags;
  73. };
  74. struct sdram_timing {
  75. u32 wrdtr;
  76. u32 clktr;
  77. };
  78. struct sdram_timing_clks {
  79. u32 wrdtr;
  80. u32 clktr;
  81. u32 rdcc;
  82. u32 flags;
  83. };
  84. struct autocal_clks {
  85. struct sdram_timing_clks clocks;
  86. struct ddrautocal autocal;
  87. };
  88. /*--------------------------------------------------------------------------+
  89. * Prototypes
  90. *--------------------------------------------------------------------------*/
  91. #if defined(CONFIG_PPC4xx_DDR_METHOD_A)
  92. static u32 DQS_calibration_methodA(struct ddrautocal *);
  93. static u32 program_DQS_calibration_methodA(struct ddrautocal *);
  94. #else
  95. static u32 DQS_calibration_methodB(struct ddrautocal *);
  96. static u32 program_DQS_calibration_methodB(struct ddrautocal *);
  97. #endif
  98. static int short_mem_test(u32 *);
  99. /*
  100. * To provide an interface for board specific config values in this common
  101. * DDR setup code, we implement he "weak" default functions here. They return
  102. * the default value back to the caller.
  103. *
  104. * Please see include/configs/yucca.h for an example fora board specific
  105. * implementation.
  106. */
  107. #if !defined(CONFIG_SPD_EEPROM)
  108. u32 __ddr_wrdtr(u32 default_val)
  109. {
  110. return default_val;
  111. }
  112. u32 ddr_wrdtr(u32) __attribute__((weak, alias("__ddr_wrdtr")));
  113. u32 __ddr_clktr(u32 default_val)
  114. {
  115. return default_val;
  116. }
  117. u32 ddr_clktr(u32) __attribute__((weak, alias("__ddr_clktr")));
  118. /*
  119. * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed
  120. */
  121. void __spd_ddr_init_hang(void)
  122. {
  123. hang();
  124. }
  125. void
  126. spd_ddr_init_hang(void) __attribute__((weak, alias("__spd_ddr_init_hang")));
  127. #endif /* defined(CONFIG_SPD_EEPROM) */
  128. ulong __ddr_scan_option(ulong default_val)
  129. {
  130. return default_val;
  131. }
  132. ulong ddr_scan_option(ulong) __attribute__((weak, alias("__ddr_scan_option")));
  133. u32 __ddr_rdss_opt(u32 default_val)
  134. {
  135. return default_val;
  136. }
  137. u32 ddr_rdss_opt(ulong) __attribute__((weak, alias("__ddr_rdss_opt")));
  138. static u32 *get_membase(int bxcr_num)
  139. {
  140. ulong bxcf;
  141. u32 *membase;
  142. #if defined(SDRAM_R0BAS)
  143. /* BAS from Memory Queue rank reg. */
  144. membase =
  145. (u32 *)(SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+bxcr_num)));
  146. bxcf = 0; /* just to satisfy the compiler */
  147. #else
  148. /* BAS from SDRAM_MBxCF mem rank reg. */
  149. mfsdram(SDRAM_MB0CF + (bxcr_num<<2), bxcf);
  150. membase = (u32 *)((bxcf & 0xfff80000) << 3);
  151. #endif
  152. return membase;
  153. }
  154. static inline void ecc_clear_status_reg(void)
  155. {
  156. mtsdram(SDRAM_ECCES, 0xffffffff);
  157. #if defined(SDRAM_R0BAS)
  158. mtdcr(SDRAM_ERRSTATLL, 0xffffffff);
  159. #endif
  160. }
  161. /*
  162. * Reset and relock memory DLL after SDRAM_CLKTR change
  163. */
  164. static inline void relock_memory_DLL(void)
  165. {
  166. u32 reg;
  167. mtsdram(SDRAM_MCOPT2, SDRAM_MCOPT2_IPTR_EXECUTE);
  168. do {
  169. mfsdram(SDRAM_MCSTAT, reg);
  170. } while (!(reg & SDRAM_MCSTAT_MIC_COMP));
  171. mfsdram(SDRAM_MCOPT2, reg);
  172. mtsdram(SDRAM_MCOPT2, reg | SDRAM_MCOPT2_DCEN_ENABLE);
  173. }
  174. static int ecc_check_status_reg(void)
  175. {
  176. u32 ecc_status;
  177. /*
  178. * Compare suceeded, now check
  179. * if got ecc error. If got an
  180. * ecc error, then don't count
  181. * this as a passing value
  182. */
  183. mfsdram(SDRAM_ECCES, ecc_status);
  184. if (ecc_status != 0x00000000) {
  185. /* clear on error */
  186. ecc_clear_status_reg();
  187. /* ecc check failure */
  188. return 0;
  189. }
  190. ecc_clear_status_reg();
  191. sync();
  192. return 1;
  193. }
  194. /* return 1 if passes, 0 if fail */
  195. static int short_mem_test(u32 *base_address)
  196. {
  197. int i, j, l;
  198. u32 ecc_mode = 0;
  199. ulong test[NUMMEMTESTS][NUMMEMWORDS] = {
  200. /* 0 */ {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
  201. 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
  202. 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
  203. 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
  204. /* 1 */ {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
  205. 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
  206. 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
  207. 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
  208. /* 2 */ {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
  209. 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
  210. 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
  211. 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
  212. /* 3 */ {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
  213. 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
  214. 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
  215. 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
  216. /* 4 */ {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
  217. 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
  218. 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
  219. 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
  220. /* 5 */ {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
  221. 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
  222. 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
  223. 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
  224. /* 6 */ {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
  225. 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
  226. 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
  227. 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
  228. /* 7 */ {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
  229. 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
  230. 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
  231. 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55},
  232. #if defined(CONFIG_SYS_DECREMENT_PATTERNS)
  233. /* 8 */ {0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
  234. 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
  235. 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
  236. 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff},
  237. /* 9 */ {0xfffefffe, 0xfffefffe, 0xfffefffe, 0xfffefffe,
  238. 0xfffefffe, 0xfffefffe, 0xfffefffe, 0xfffefffe,
  239. 0xfffefffe, 0xfffefffe, 0xfffefffe, 0xfffefffe,
  240. 0xfffefffe, 0xfffefffe, 0xfffefffe, 0xfffefffe},
  241. /* 10 */{0xfffdfffd, 0xfffdfffd, 0xfffdffff, 0xfffdfffd,
  242. 0xfffdfffd, 0xfffdfffd, 0xfffdffff, 0xfffdfffd,
  243. 0xfffdfffd, 0xfffdfffd, 0xfffdffff, 0xfffdfffd,
  244. 0xfffdfffd, 0xfffdfffd, 0xfffdffff, 0xfffdfffd},
  245. /* 11 */{0xfffcfffc, 0xfffcfffc, 0xfffcfffc, 0xfffcfffc,
  246. 0xfffcfffc, 0xfffcfffc, 0xfffcfffc, 0xfffcfffc,
  247. 0xfffcfffc, 0xfffcfffc, 0xfffcfffc, 0xfffcfffc,
  248. 0xfffcfffc, 0xfffcfffc, 0xfffcfffc, 0xfffcfffc},
  249. /* 12 */{0xfffbfffb, 0xfffffffb, 0xfffffffb, 0xfffffffb,
  250. 0xfffbfffb, 0xfffffffb, 0xfffffffb, 0xfffffffb,
  251. 0xfffbfffb, 0xfffffffb, 0xfffffffb, 0xfffffffb,
  252. 0xfffbfffb, 0xfffffffb, 0xfffffffb, 0xfffffffb},
  253. /* 13 */{0xfffafffa, 0xfffafffa, 0xfffffffa, 0xfffafffa,
  254. 0xfffafffa, 0xfffafffa, 0xfffafffa, 0xfffafffa,
  255. 0xfffafffa, 0xfffafffa, 0xfffafffa, 0xfffafffa,
  256. 0xfffafffa, 0xfffafffa, 0xfffafffa, 0xfffafffa},
  257. /* 14 */{0xfff9fff9, 0xfff9fff9, 0xfff9fff9, 0xfff9fff9,
  258. 0xfff9fff9, 0xfff9fff9, 0xfff9fff9, 0xfff9fff9,
  259. 0xfff9fff9, 0xfff9fff9, 0xfff9fff9, 0xfff9fff9,
  260. 0xfff9fff9, 0xfff9fff9, 0xfff9fff9, 0xfff9fff9},
  261. /* 15 */{0xfff8fff8, 0xfff8fff8, 0xfff8fff8, 0xfff8fff8,
  262. 0xfff8fff8, 0xfff8fff8, 0xfff8fff8, 0xfff8fff8,
  263. 0xfff8fff8, 0xfff8fff8, 0xfff8fff8, 0xfff8fff8,
  264. 0xfff8fff8, 0xfff8fff8, 0xfff8fff8, 0xfff8fff8},
  265. /* 16 */{0xfff7fff7, 0xfff7ffff, 0xfff7fff7, 0xfff7fff7,
  266. 0xfff7fff7, 0xfff7ffff, 0xfff7fff7, 0xfff7fff7,
  267. 0xfff7fff7, 0xfff7ffff, 0xfff7fff7, 0xfff7fff7,
  268. 0xfff7ffff, 0xfff7ffff, 0xfff7fff7, 0xfff7fff7},
  269. /* 17 */{0xfff6fff5, 0xfff6ffff, 0xfff6fff6, 0xfff6fff7,
  270. 0xfff6fff5, 0xfff6ffff, 0xfff6fff6, 0xfff6fff7,
  271. 0xfff6fff5, 0xfff6ffff, 0xfff6fff6, 0xfff6fff7,
  272. 0xfff6fff5, 0xfff6ffff, 0xfff6fff6, 0xfff6fff7},
  273. /* 18 */{0xfff5fff4, 0xfff5ffff, 0xfff5fff5, 0xfff5fff5,
  274. 0xfff5fff4, 0xfff5ffff, 0xfff5fff5, 0xfff5fff5,
  275. 0xfff5fff4, 0xfff5ffff, 0xfff5fff5, 0xfff5fff5,
  276. 0xfff5fff4, 0xfff5ffff, 0xfff5fff5, 0xfff5fff5},
  277. /* 19 */{0xfff4fff3, 0xfff4ffff, 0xfff4fff4, 0xfff4fff4,
  278. 0xfff4fff3, 0xfff4ffff, 0xfff4fff4, 0xfff4fff4,
  279. 0xfff4fff3, 0xfff4ffff, 0xfff4fff4, 0xfff4fff4,
  280. 0xfff4fff3, 0xfff4ffff, 0xfff4fff4, 0xfff4fff4},
  281. /* 20 */{0xfff3fff2, 0xfff3ffff, 0xfff3fff3, 0xfff3fff3,
  282. 0xfff3fff2, 0xfff3ffff, 0xfff3fff3, 0xfff3fff3,
  283. 0xfff3fff2, 0xfff3ffff, 0xfff3fff3, 0xfff3fff3,
  284. 0xfff3fff2, 0xfff3ffff, 0xfff3fff3, 0xfff3fff3},
  285. /* 21 */{0xfff2ffff, 0xfff2ffff, 0xfff2fff2, 0xfff2fff2,
  286. 0xfff2ffff, 0xfff2ffff, 0xfff2fff2, 0xfff2fff2,
  287. 0xfff2ffff, 0xfff2ffff, 0xfff2fff2, 0xfff2fff2,
  288. 0xfff2ffff, 0xfff2ffff, 0xfff2fff2, 0xfff2fff2},
  289. /* 22 */{0xfff1ffff, 0xfff1ffff, 0xfff1fff1, 0xfff1fff1,
  290. 0xfff1ffff, 0xfff1ffff, 0xfff1fff1, 0xfff1fff1,
  291. 0xfff1ffff, 0xfff1ffff, 0xfff1fff1, 0xfff1fff1,
  292. 0xfff1ffff, 0xfff1ffff, 0xfff1fff1, 0xfff1fff1},
  293. /* 23 */{0xfff0fff0, 0xfff0fff0, 0xfff0fff0, 0xfff0fff0,
  294. 0xfff0fff0, 0xfff0fff0, 0xfff0fff0, 0xfff0fff0,
  295. 0xfff0fff0, 0xfff0fff0, 0xfff0fff0, 0xfff0fff0,
  296. 0xfff0fff0, 0xfff0fffe, 0xfff0fff0, 0xfff0fff0},
  297. #endif /* CONFIG_SYS_DECREMENT_PATTERNS */
  298. };
  299. mfsdram(SDRAM_MCOPT1, ecc_mode);
  300. if ((ecc_mode & SDRAM_MCOPT1_MCHK_CHK_REP) ==
  301. SDRAM_MCOPT1_MCHK_CHK_REP) {
  302. ecc_clear_status_reg();
  303. sync();
  304. ecc_mode = 1;
  305. } else {
  306. ecc_mode = 0;
  307. }
  308. /*
  309. * Run the short memory test.
  310. */
  311. for (i = 0; i < NUMMEMTESTS; i++) {
  312. for (j = 0; j < NUMMEMWORDS; j++) {
  313. base_address[j] = test[i][j];
  314. ppcDcbf((ulong)&(base_address[j]));
  315. }
  316. sync();
  317. iobarrier_rw();
  318. for (l = 0; l < NUMLOOPS; l++) {
  319. for (j = 0; j < NUMMEMWORDS; j++) {
  320. if (base_address[j] != test[i][j]) {
  321. ppcDcbf((u32)&(base_address[j]));
  322. return 0;
  323. } else {
  324. if (ecc_mode) {
  325. if (!ecc_check_status_reg())
  326. return 0;
  327. }
  328. }
  329. ppcDcbf((u32)&(base_address[j]));
  330. } /* for (j = 0; j < NUMMEMWORDS; j++) */
  331. sync();
  332. iobarrier_rw();
  333. } /* for (l=0; l<NUMLOOPS; l++) */
  334. }
  335. return 1;
  336. }
  337. #if defined(CONFIG_PPC4xx_DDR_METHOD_A)
  338. /*-----------------------------------------------------------------------------+
  339. | program_DQS_calibration_methodA.
  340. +-----------------------------------------------------------------------------*/
  341. static u32 program_DQS_calibration_methodA(struct ddrautocal *ddrcal)
  342. {
  343. u32 pass_result = 0;
  344. #ifdef DEBUG
  345. ulong temp;
  346. mfsdram(SDRAM_RDCC, temp);
  347. debug("<%s>SDRAM_RDCC=0x%08x\n", __func__, temp);
  348. #endif
  349. pass_result = DQS_calibration_methodA(ddrcal);
  350. return pass_result;
  351. }
  352. /*
  353. * DQS_calibration_methodA()
  354. *
  355. * Autocalibration Method A
  356. *
  357. * ARRAY [Entire DQS Range] DQS_Valid_Window ; initialized to all zeros
  358. * ARRAY [Entire FDBK Range] FDBK_Valid_Window; initialized to all zeros
  359. * MEMWRITE(addr, expected_data);
  360. * for (i = 0; i < Entire DQS Range; i++) { RQDC.RQFD
  361. * for (j = 0; j < Entire FDBK Range; j++) { RFDC.RFFD
  362. * MEMREAD(addr, actual_data);
  363. * if (actual_data == expected_data) {
  364. * DQS_Valid_Window[i] = 1; RQDC.RQFD
  365. * FDBK_Valid_Window[i][j] = 1; RFDC.RFFD
  366. * }
  367. * }
  368. * }
  369. */
  370. static u32 DQS_calibration_methodA(struct ddrautocal *cal)
  371. {
  372. ulong rfdc_reg;
  373. ulong rffd;
  374. ulong rqdc_reg;
  375. ulong rqfd;
  376. u32 *membase;
  377. ulong bxcf;
  378. int rqfd_average;
  379. int bxcr_num;
  380. int rffd_average;
  381. int pass;
  382. u32 passed = 0;
  383. int in_window;
  384. struct autocal_regs curr_win_min;
  385. struct autocal_regs curr_win_max;
  386. struct autocal_regs best_win_min;
  387. struct autocal_regs best_win_max;
  388. struct autocal_regs loop_win_min;
  389. struct autocal_regs loop_win_max;
  390. #ifdef DEBUG
  391. ulong temp;
  392. #endif
  393. ulong rdcc;
  394. char slash[] = "\\|/-\\|/-";
  395. int loopi = 0;
  396. /* start */
  397. in_window = 0;
  398. memset(&curr_win_min, 0, sizeof(curr_win_min));
  399. memset(&curr_win_max, 0, sizeof(curr_win_max));
  400. memset(&best_win_min, 0, sizeof(best_win_min));
  401. memset(&best_win_max, 0, sizeof(best_win_max));
  402. memset(&loop_win_min, 0, sizeof(loop_win_min));
  403. memset(&loop_win_max, 0, sizeof(loop_win_max));
  404. rdcc = 0;
  405. /*
  406. * Program RDCC register
  407. * Read sample cycle auto-update enable
  408. */
  409. mtsdram(SDRAM_RDCC,
  410. ddr_rdss_opt(SDRAM_RDCC_RDSS_T2) | SDRAM_RDCC_RSAE_ENABLE);
  411. #ifdef DEBUG
  412. mfsdram(SDRAM_RDCC, temp);
  413. debug("<%s>SDRAM_RDCC=0x%x\n", __func__, temp);
  414. mfsdram(SDRAM_RTSR, temp);
  415. debug("<%s>SDRAM_RTSR=0x%x\n", __func__, temp);
  416. mfsdram(SDRAM_FCSR, temp);
  417. debug("<%s>SDRAM_FCSR=0x%x\n", __func__, temp);
  418. #endif
  419. /*
  420. * Program RQDC register
  421. * Internal DQS delay mechanism enable
  422. */
  423. mtsdram(SDRAM_RQDC,
  424. SDRAM_RQDC_RQDE_ENABLE | SDRAM_RQDC_RQFD_ENCODE(0x00));
  425. #ifdef DEBUG
  426. mfsdram(SDRAM_RQDC, temp);
  427. debug("<%s>SDRAM_RQDC=0x%x\n", __func__, temp);
  428. #endif
  429. /*
  430. * Program RFDC register
  431. * Set Feedback Fractional Oversample
  432. * Auto-detect read sample cycle enable
  433. */
  434. mtsdram(SDRAM_RFDC, SDRAM_RFDC_ARSE_ENABLE |
  435. SDRAM_RFDC_RFOS_ENCODE(0) | SDRAM_RFDC_RFFD_ENCODE(0));
  436. #ifdef DEBUG
  437. mfsdram(SDRAM_RFDC, temp);
  438. debug("<%s>SDRAM_RFDC=0x%x\n", __func__, temp);
  439. #endif
  440. putc(' ');
  441. for (rqfd = 0; rqfd <= SDRAM_RQDC_RQFD_MAX; rqfd++) {
  442. mfsdram(SDRAM_RQDC, rqdc_reg);
  443. rqdc_reg &= ~(SDRAM_RQDC_RQFD_MASK);
  444. mtsdram(SDRAM_RQDC, rqdc_reg | SDRAM_RQDC_RQFD_ENCODE(rqfd));
  445. putc('\b');
  446. putc(slash[loopi++ % 8]);
  447. curr_win_min.rffd = 0;
  448. curr_win_max.rffd = 0;
  449. in_window = 0;
  450. for (rffd = 0, pass = 0; rffd <= SDRAM_RFDC_RFFD_MAX; rffd++) {
  451. mfsdram(SDRAM_RFDC, rfdc_reg);
  452. rfdc_reg &= ~(SDRAM_RFDC_RFFD_MASK);
  453. mtsdram(SDRAM_RFDC,
  454. rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd));
  455. for (bxcr_num = 0; bxcr_num < MAXBXCF; bxcr_num++) {
  456. mfsdram(SDRAM_MB0CF + (bxcr_num<<2), bxcf);
  457. /* Banks enabled */
  458. if (bxcf & SDRAM_BXCF_M_BE_MASK) {
  459. /* Bank is enabled */
  460. membase = get_membase(bxcr_num);
  461. pass = short_mem_test(membase);
  462. } /* if bank enabled */
  463. } /* for bxcr_num */
  464. /* If this value passed update RFFD windows */
  465. if (pass && !in_window) { /* at the start of window */
  466. in_window = 1;
  467. curr_win_min.rffd = curr_win_max.rffd = rffd;
  468. curr_win_min.rqfd = curr_win_max.rqfd = rqfd;
  469. mfsdram(SDRAM_RDCC, rdcc); /*record this value*/
  470. } else if (!pass && in_window) { /* at end of window */
  471. in_window = 0;
  472. } else if (pass && in_window) { /* within the window */
  473. curr_win_max.rffd = rffd;
  474. curr_win_max.rqfd = rqfd;
  475. }
  476. /* else if (!pass && !in_window)
  477. skip - no pass, not currently in a window */
  478. if (in_window) {
  479. if ((curr_win_max.rffd - curr_win_min.rffd) >
  480. (best_win_max.rffd - best_win_min.rffd)) {
  481. best_win_min.rffd = curr_win_min.rffd;
  482. best_win_max.rffd = curr_win_max.rffd;
  483. best_win_min.rqfd = curr_win_min.rqfd;
  484. best_win_max.rqfd = curr_win_max.rqfd;
  485. cal->rdcc = rdcc;
  486. }
  487. passed = 1;
  488. }
  489. } /* RFDC.RFFD */
  490. /*
  491. * save-off the best window results of the RFDC.RFFD
  492. * for this RQDC.RQFD setting
  493. */
  494. /*
  495. * if (just ended RFDC.RFDC loop pass window) >
  496. * (prior RFDC.RFFD loop pass window)
  497. */
  498. if ((best_win_max.rffd - best_win_min.rffd) >
  499. (loop_win_max.rffd - loop_win_min.rffd)) {
  500. loop_win_min.rffd = best_win_min.rffd;
  501. loop_win_max.rffd = best_win_max.rffd;
  502. loop_win_min.rqfd = rqfd;
  503. loop_win_max.rqfd = rqfd;
  504. debug("RQFD.min 0x%08x, RQFD.max 0x%08x, "
  505. "RFFD.min 0x%08x, RFFD.max 0x%08x\n",
  506. loop_win_min.rqfd, loop_win_max.rqfd,
  507. loop_win_min.rffd, loop_win_max.rffd);
  508. }
  509. } /* RQDC.RQFD */
  510. putc('\b');
  511. debug("\n");
  512. if ((loop_win_min.rffd == 0) && (loop_win_max.rffd == 0) &&
  513. (best_win_min.rffd == 0) && (best_win_max.rffd == 0) &&
  514. (best_win_min.rqfd == 0) && (best_win_max.rqfd == 0)) {
  515. passed = 0;
  516. }
  517. /*
  518. * Need to program RQDC before RFDC.
  519. */
  520. debug("<%s> RQFD Min: 0x%x\n", __func__, loop_win_min.rqfd);
  521. debug("<%s> RQFD Max: 0x%x\n", __func__, loop_win_max.rqfd);
  522. rqfd_average = loop_win_max.rqfd;
  523. if (rqfd_average < 0)
  524. rqfd_average = 0;
  525. if (rqfd_average > SDRAM_RQDC_RQFD_MAX)
  526. rqfd_average = SDRAM_RQDC_RQFD_MAX;
  527. debug("<%s> RFFD average: 0x%08x\n", __func__, rqfd_average);
  528. mtsdram(SDRAM_RQDC, (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
  529. SDRAM_RQDC_RQFD_ENCODE(rqfd_average));
  530. debug("<%s> RFFD Min: 0x%08x\n", __func__, loop_win_min.rffd);
  531. debug("<%s> RFFD Max: 0x%08x\n", __func__, loop_win_max.rffd);
  532. rffd_average = ((loop_win_min.rffd + loop_win_max.rffd) / 2);
  533. if (rffd_average < 0)
  534. rffd_average = 0;
  535. if (rffd_average > SDRAM_RFDC_RFFD_MAX)
  536. rffd_average = SDRAM_RFDC_RFFD_MAX;
  537. debug("<%s> RFFD average: 0x%08x\n", __func__, rffd_average);
  538. mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd_average));
  539. /* if something passed, then return the size of the largest window */
  540. if (passed != 0) {
  541. passed = loop_win_max.rffd - loop_win_min.rffd;
  542. cal->rqfd = rqfd_average;
  543. cal->rffd = rffd_average;
  544. cal->rffd_min = loop_win_min.rffd;
  545. cal->rffd_max = loop_win_max.rffd;
  546. }
  547. return (u32)passed;
  548. }
  549. #else /* !defined(CONFIG_PPC4xx_DDR_METHOD_A) */
  550. /*-----------------------------------------------------------------------------+
  551. | program_DQS_calibration_methodB.
  552. +-----------------------------------------------------------------------------*/
  553. static u32 program_DQS_calibration_methodB(struct ddrautocal *ddrcal)
  554. {
  555. u32 pass_result = 0;
  556. #ifdef DEBUG
  557. ulong temp;
  558. #endif
  559. /*
  560. * Program RDCC register
  561. * Read sample cycle auto-update enable
  562. */
  563. mtsdram(SDRAM_RDCC,
  564. ddr_rdss_opt(SDRAM_RDCC_RDSS_T2) | SDRAM_RDCC_RSAE_ENABLE);
  565. #ifdef DEBUG
  566. mfsdram(SDRAM_RDCC, temp);
  567. debug("<%s>SDRAM_RDCC=0x%08x\n", __func__, temp);
  568. #endif
  569. /*
  570. * Program RQDC register
  571. * Internal DQS delay mechanism enable
  572. */
  573. mtsdram(SDRAM_RQDC,
  574. #if defined(CONFIG_DDR_RQDC_START_VAL)
  575. SDRAM_RQDC_RQDE_ENABLE |
  576. SDRAM_RQDC_RQFD_ENCODE(CONFIG_DDR_RQDC_START_VAL));
  577. #else
  578. SDRAM_RQDC_RQDE_ENABLE | SDRAM_RQDC_RQFD_ENCODE(0x38));
  579. #endif
  580. #ifdef DEBUG
  581. mfsdram(SDRAM_RQDC, temp);
  582. debug("<%s>SDRAM_RQDC=0x%08x\n", __func__, temp);
  583. #endif
  584. /*
  585. * Program RFDC register
  586. * Set Feedback Fractional Oversample
  587. * Auto-detect read sample cycle enable
  588. */
  589. mtsdram(SDRAM_RFDC, SDRAM_RFDC_ARSE_ENABLE |
  590. SDRAM_RFDC_RFOS_ENCODE(0) |
  591. SDRAM_RFDC_RFFD_ENCODE(0));
  592. #ifdef DEBUG
  593. mfsdram(SDRAM_RFDC, temp);
  594. debug("<%s>SDRAM_RFDC=0x%08x\n", __func__, temp);
  595. #endif
  596. pass_result = DQS_calibration_methodB(ddrcal);
  597. return pass_result;
  598. }
  599. /*
  600. * DQS_calibration_methodB()
  601. *
  602. * Autocalibration Method B
  603. *
  604. * ARRAY [Entire DQS Range] DQS_Valid_Window ; initialized to all zeros
  605. * ARRAY [Entire Feedback Range] FDBK_Valid_Window; initialized to all zeros
  606. * MEMWRITE(addr, expected_data);
  607. * Initialialize the DQS delay to 80 degrees (MCIF0_RRQDC[RQFD]=0x38).
  608. *
  609. * for (j = 0; j < Entire Feedback Range; j++) {
  610. * MEMREAD(addr, actual_data);
  611. * if (actual_data == expected_data) {
  612. * FDBK_Valid_Window[j] = 1;
  613. * }
  614. * }
  615. *
  616. * Set MCIF0_RFDC[RFFD] to the middle of the FDBK_Valid_Window.
  617. *
  618. * for (i = 0; i < Entire DQS Range; i++) {
  619. * MEMREAD(addr, actual_data);
  620. * if (actual_data == expected_data) {
  621. * DQS_Valid_Window[i] = 1;
  622. * }
  623. * }
  624. *
  625. * Set MCIF0_RRQDC[RQFD] to the middle of the DQS_Valid_Window.
  626. */
  627. /*-----------------------------------------------------------------------------+
  628. | DQS_calibration_methodB.
  629. +-----------------------------------------------------------------------------*/
  630. static u32 DQS_calibration_methodB(struct ddrautocal *cal)
  631. {
  632. ulong rfdc_reg;
  633. ulong rffd;
  634. ulong rqdc_reg;
  635. ulong rqfd;
  636. ulong rdcc;
  637. u32 *membase;
  638. ulong bxcf;
  639. int rqfd_average;
  640. int bxcr_num;
  641. int rffd_average;
  642. int pass;
  643. uint passed = 0;
  644. int in_window;
  645. u32 curr_win_min, curr_win_max;
  646. u32 best_win_min, best_win_max;
  647. u32 size = 0;
  648. /*------------------------------------------------------------------
  649. | Test to determine the best read clock delay tuning bits.
  650. |
  651. | Before the DDR controller can be used, the read clock delay needs to
  652. | be set. This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
  653. | This value cannot be hardcoded into the program because it changes
  654. | depending on the board's setup and environment.
  655. | To do this, all delay values are tested to see if they
  656. | work or not. By doing this, you get groups of fails with groups of
  657. | passing values. The idea is to find the start and end of a passing
  658. | window and take the center of it to use as the read clock delay.
  659. |
  660. | A failure has to be seen first so that when we hit a pass, we know
  661. | that it is truely the start of the window. If we get passing values
  662. | to start off with, we don't know if we are at the start of the window
  663. |
  664. | The code assumes that a failure will always be found.
  665. | If a failure is not found, there is no easy way to get the middle
  666. | of the passing window. I guess we can pretty much pick any value
  667. | but some values will be better than others. Since the lowest speed
  668. | we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
  669. | from experimentation it is safe to say you will always have a failure
  670. +-----------------------------------------------------------------*/
  671. debug("\n\n");
  672. in_window = 0;
  673. rdcc = 0;
  674. curr_win_min = curr_win_max = 0;
  675. best_win_min = best_win_max = 0;
  676. for (rffd = 0; rffd <= SDRAM_RFDC_RFFD_MAX; rffd++) {
  677. mfsdram(SDRAM_RFDC, rfdc_reg);
  678. rfdc_reg &= ~(SDRAM_RFDC_RFFD_MASK);
  679. mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd));
  680. pass = 1;
  681. for (bxcr_num = 0; bxcr_num < MAXBXCF; bxcr_num++) {
  682. mfsdram(SDRAM_MB0CF + (bxcr_num<<2), bxcf);
  683. /* Banks enabled */
  684. if (bxcf & SDRAM_BXCF_M_BE_MASK) {
  685. /* Bank is enabled */
  686. membase = get_membase(bxcr_num);
  687. pass &= short_mem_test(membase);
  688. } /* if bank enabled */
  689. } /* for bxcf_num */
  690. /* If this value passed */
  691. if (pass && !in_window) { /* start of passing window */
  692. in_window = 1;
  693. curr_win_min = curr_win_max = rffd;
  694. mfsdram(SDRAM_RDCC, rdcc); /* record this value */
  695. } else if (!pass && in_window) { /* end passing window */
  696. in_window = 0;
  697. } else if (pass && in_window) { /* within the passing window */
  698. curr_win_max = rffd;
  699. }
  700. if (in_window) {
  701. if ((curr_win_max - curr_win_min) >
  702. (best_win_max - best_win_min)) {
  703. best_win_min = curr_win_min;
  704. best_win_max = curr_win_max;
  705. cal->rdcc = rdcc;
  706. }
  707. passed = 1;
  708. }
  709. } /* for rffd */
  710. if ((best_win_min == 0) && (best_win_max == 0))
  711. passed = 0;
  712. else
  713. size = best_win_max - best_win_min;
  714. debug("RFFD Min: 0x%x\n", best_win_min);
  715. debug("RFFD Max: 0x%x\n", best_win_max);
  716. rffd_average = ((best_win_min + best_win_max) / 2);
  717. cal->rffd_min = best_win_min;
  718. cal->rffd_max = best_win_max;
  719. if (rffd_average < 0)
  720. rffd_average = 0;
  721. if (rffd_average > SDRAM_RFDC_RFFD_MAX)
  722. rffd_average = SDRAM_RFDC_RFFD_MAX;
  723. mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd_average));
  724. rffd = rffd_average;
  725. in_window = 0;
  726. curr_win_min = curr_win_max = 0;
  727. best_win_min = best_win_max = 0;
  728. for (rqfd = 0; rqfd <= SDRAM_RQDC_RQFD_MAX; rqfd++) {
  729. mfsdram(SDRAM_RQDC, rqdc_reg);
  730. rqdc_reg &= ~(SDRAM_RQDC_RQFD_MASK);
  731. mtsdram(SDRAM_RQDC, rqdc_reg | SDRAM_RQDC_RQFD_ENCODE(rqfd));
  732. pass = 1;
  733. for (bxcr_num = 0; bxcr_num < MAXBXCF; bxcr_num++) {
  734. mfsdram(SDRAM_MB0CF + (bxcr_num<<2), bxcf);
  735. /* Banks enabled */
  736. if (bxcf & SDRAM_BXCF_M_BE_MASK) {
  737. /* Bank is enabled */
  738. membase = get_membase(bxcr_num);
  739. pass &= short_mem_test(membase);
  740. } /* if bank enabled */
  741. } /* for bxcf_num */
  742. /* If this value passed */
  743. if (pass && !in_window) {
  744. in_window = 1;
  745. curr_win_min = curr_win_max = rqfd;
  746. } else if (!pass && in_window) {
  747. in_window = 0;
  748. } else if (pass && in_window) {
  749. curr_win_max = rqfd;
  750. }
  751. if (in_window) {
  752. if ((curr_win_max - curr_win_min) >
  753. (best_win_max - best_win_min)) {
  754. best_win_min = curr_win_min;
  755. best_win_max = curr_win_max;
  756. }
  757. passed = 1;
  758. }
  759. } /* for rqfd */
  760. if ((best_win_min == 0) && (best_win_max == 0))
  761. passed = 0;
  762. debug("RQFD Min: 0x%x\n", best_win_min);
  763. debug("RQFD Max: 0x%x\n", best_win_max);
  764. rqfd_average = ((best_win_min + best_win_max) / 2);
  765. if (rqfd_average < 0)
  766. rqfd_average = 0;
  767. if (rqfd_average > SDRAM_RQDC_RQFD_MAX)
  768. rqfd_average = SDRAM_RQDC_RQFD_MAX;
  769. mtsdram(SDRAM_RQDC, (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
  770. SDRAM_RQDC_RQFD_ENCODE(rqfd_average));
  771. mfsdram(SDRAM_RQDC, rqdc_reg);
  772. mfsdram(SDRAM_RFDC, rfdc_reg);
  773. /*
  774. * Need to program RQDC before RFDC. The value is read above.
  775. * That is the reason why auto cal not work.
  776. * See, comments below.
  777. */
  778. mtsdram(SDRAM_RQDC, rqdc_reg);
  779. mtsdram(SDRAM_RFDC, rfdc_reg);
  780. debug("RQDC: 0x%08X\n", rqdc_reg);
  781. debug("RFDC: 0x%08X\n", rfdc_reg);
  782. /* if something passed, then return the size of the largest window */
  783. if (passed != 0) {
  784. passed = size;
  785. cal->rqfd = rqfd_average;
  786. cal->rffd = rffd_average;
  787. }
  788. return (uint)passed;
  789. }
  790. #endif /* defined(CONFIG_PPC4xx_DDR_METHOD_A) */
  791. /*
  792. * Default table for DDR auto-calibration of all
  793. * possible WRDTR and CLKTR values.
  794. * Table format is:
  795. * {SDRAM_WRDTR.[WDTR], SDRAM_CLKTR.[CKTR]}
  796. *
  797. * Table is terminated with {-1, -1} value pair.
  798. *
  799. * Board vendors can specify their own board specific subset of
  800. * known working {SDRAM_WRDTR.[WDTR], SDRAM_CLKTR.[CKTR]} value
  801. * pairs via a board defined ddr_scan_option() function.
  802. */
  803. struct sdram_timing full_scan_options[] = {
  804. {0, 0}, {0, 1}, {0, 2}, {0, 3},
  805. {1, 0}, {1, 1}, {1, 2}, {1, 3},
  806. {2, 0}, {2, 1}, {2, 2}, {2, 3},
  807. {3, 0}, {3, 1}, {3, 2}, {3, 3},
  808. {4, 0}, {4, 1}, {4, 2}, {4, 3},
  809. {5, 0}, {5, 1}, {5, 2}, {5, 3},
  810. {6, 0}, {6, 1}, {6, 2}, {6, 3},
  811. {-1, -1}
  812. };
  813. /*---------------------------------------------------------------------------+
  814. | DQS_calibration.
  815. +----------------------------------------------------------------------------*/
  816. u32 DQS_autocalibration(void)
  817. {
  818. u32 wdtr;
  819. u32 clkp;
  820. u32 result = 0;
  821. u32 best_result = 0;
  822. u32 best_rdcc;
  823. struct ddrautocal ddrcal;
  824. struct autocal_clks tcal;
  825. ulong rfdc_reg;
  826. ulong rqdc_reg;
  827. u32 val;
  828. int verbose_lvl = 0;
  829. char *str;
  830. char slash[] = "\\|/-\\|/-";
  831. int loopi = 0;
  832. struct sdram_timing *scan_list;
  833. #if defined(DEBUG_PPC4xx_DDR_AUTOCALIBRATION)
  834. int i;
  835. char tmp[64]; /* long enough for environment variables */
  836. #endif
  837. memset(&tcal, 0, sizeof(tcal));
  838. ddr_scan_option((ulong)full_scan_options);
  839. scan_list =
  840. (struct sdram_timing *)ddr_scan_option((ulong)full_scan_options);
  841. mfsdram(SDRAM_MCOPT1, val);
  842. if ((val & SDRAM_MCOPT1_MCHK_CHK_REP) == SDRAM_MCOPT1_MCHK_CHK_REP)
  843. str = "ECC Auto calibration -";
  844. else
  845. str = "Auto calibration -";
  846. puts(str);
  847. #if defined(DEBUG_PPC4xx_DDR_AUTOCALIBRATION)
  848. i = getenv_r("autocalib", tmp, sizeof(tmp));
  849. if (i < 0)
  850. strcpy(tmp, CONFIG_AUTOCALIB);
  851. if (strcmp(tmp, "final") == 0) {
  852. /* display the final autocalibration results only */
  853. verbose_lvl = 1;
  854. } else if (strcmp(tmp, "loop") == 0) {
  855. /* display summary autocalibration info per iteration */
  856. verbose_lvl = 2;
  857. } else if (strcmp(tmp, "display") == 0) {
  858. /* display full debug autocalibration window info. */
  859. verbose_lvl = 3;
  860. }
  861. #endif /* (DEBUG_PPC4xx_DDR_AUTOCALIBRATION) */
  862. best_rdcc = (SDRAM_RDCC_RDSS_T4 >> 30);
  863. while ((scan_list->wrdtr != -1) && (scan_list->clktr != -1)) {
  864. wdtr = scan_list->wrdtr;
  865. clkp = scan_list->clktr;
  866. mfsdram(SDRAM_WRDTR, val);
  867. val &= ~(SDRAM_WRDTR_LLWP_MASK | SDRAM_WRDTR_WTR_MASK);
  868. mtsdram(SDRAM_WRDTR, (val |
  869. ddr_wrdtr(SDRAM_WRDTR_LLWP_1_CYC | (wdtr << 25))));
  870. mtsdram(SDRAM_CLKTR, clkp << 30);
  871. relock_memory_DLL();
  872. putc('\b');
  873. putc(slash[loopi++ % 8]);
  874. #ifdef DEBUG
  875. debug("\n");
  876. debug("*** --------------\n");
  877. mfsdram(SDRAM_WRDTR, val);
  878. debug("*** SDRAM_WRDTR set to 0x%08x\n", val);
  879. mfsdram(SDRAM_CLKTR, val);
  880. debug("*** SDRAM_CLKTR set to 0x%08x\n", val);
  881. #endif
  882. debug("\n");
  883. if (verbose_lvl > 2) {
  884. printf("*** SDRAM_WRDTR (wdtr) set to %d\n", wdtr);
  885. printf("*** SDRAM_CLKTR (clkp) set to %d\n", clkp);
  886. }
  887. memset(&ddrcal, 0, sizeof(ddrcal));
  888. /*
  889. * DQS calibration.
  890. */
  891. /*
  892. * program_DQS_calibration_method[A|B]() returns 0 if no
  893. * passing RFDC.[RFFD] window is found or returns the size
  894. * of the best passing window; in the case of a found passing
  895. * window, the ddrcal will contain the values of the best
  896. * window RQDC.[RQFD] and RFDC.[RFFD].
  897. */
  898. /*
  899. * Call PPC4xx SDRAM DDR autocalibration methodA or methodB.
  900. * Default is methodB.
  901. * Defined the autocalibration method in the board specific
  902. * header file.
  903. * Please see include/configs/kilauea.h for an example for
  904. * a board specific implementation.
  905. */
  906. #if defined(CONFIG_PPC4xx_DDR_METHOD_A)
  907. result = program_DQS_calibration_methodA(&ddrcal);
  908. #else
  909. result = program_DQS_calibration_methodB(&ddrcal);
  910. #endif
  911. sync();
  912. /*
  913. * Clear potential errors resulting from auto-calibration.
  914. * If not done, then we could get an interrupt later on when
  915. * exceptions are enabled.
  916. */
  917. set_mcsr(get_mcsr());
  918. val = ddrcal.rdcc; /* RDCC from the best passing window */
  919. udelay(100);
  920. if (verbose_lvl > 1) {
  921. char *tstr;
  922. switch ((val >> 30)) {
  923. case 0:
  924. if (result != 0)
  925. tstr = "T1";
  926. else
  927. tstr = "N/A";
  928. break;
  929. case 1:
  930. tstr = "T2";
  931. break;
  932. case 2:
  933. tstr = "T3";
  934. break;
  935. case 3:
  936. tstr = "T4";
  937. break;
  938. default:
  939. tstr = "unknown";
  940. break;
  941. }
  942. printf("** WRDTR(%d) CLKTR(%d), Wind (%d), best (%d), "
  943. "max-min(0x%04x)(0x%04x), RDCC: %s\n",
  944. wdtr, clkp, result, best_result,
  945. ddrcal.rffd_min, ddrcal.rffd_max, tstr);
  946. }
  947. /*
  948. * The DQS calibration "result" is either "0"
  949. * if no passing window was found, or is the
  950. * size of the RFFD passing window.
  951. */
  952. /*
  953. * want the lowest Read Sample Cycle Select
  954. */
  955. val = SDRAM_RDCC_RDSS_DECODE(val);
  956. debug("*** (%d) (%d) current_rdcc, best_rdcc\n",
  957. val, best_rdcc);
  958. if ((result != 0) &&
  959. (val >= SDRAM_RDCC_RDSS_VAL(SDRAM_RDCC_RDSS_T2))) {
  960. if (((result == best_result) && (val < best_rdcc)) ||
  961. ((result > best_result) && (val <= best_rdcc))) {
  962. tcal.autocal.flags = 1;
  963. debug("*** (%d)(%d) result passed window "
  964. "size: 0x%08x, rqfd = 0x%08x, "
  965. "rffd = 0x%08x, rdcc = 0x%08x\n",
  966. wdtr, clkp, result, ddrcal.rqfd,
  967. ddrcal.rffd, ddrcal.rdcc);
  968. /*
  969. * Save the SDRAM_WRDTR and SDRAM_CLKTR
  970. * settings for the largest returned
  971. * RFFD passing window size.
  972. */
  973. best_rdcc = val;
  974. tcal.clocks.wrdtr = wdtr;
  975. tcal.clocks.clktr = clkp;
  976. tcal.clocks.rdcc = SDRAM_RDCC_RDSS_ENCODE(val);
  977. tcal.autocal.rqfd = ddrcal.rqfd;
  978. tcal.autocal.rffd = ddrcal.rffd;
  979. best_result = result;
  980. if (verbose_lvl > 2) {
  981. printf("** (%d)(%d) "
  982. "best result: 0x%04x\n",
  983. wdtr, clkp,
  984. best_result);
  985. printf("** (%d)(%d) "
  986. "best WRDTR: 0x%04x\n",
  987. wdtr, clkp,
  988. tcal.clocks.wrdtr);
  989. printf("** (%d)(%d) "
  990. "best CLKTR: 0x%04x\n",
  991. wdtr, clkp,
  992. tcal.clocks.clktr);
  993. printf("** (%d)(%d) "
  994. "best RQDC: 0x%04x\n",
  995. wdtr, clkp,
  996. tcal.autocal.rqfd);
  997. printf("** (%d)(%d) "
  998. "best RFDC: 0x%04x\n",
  999. wdtr, clkp,
  1000. tcal.autocal.rffd);
  1001. printf("** (%d)(%d) "
  1002. "best RDCC: 0x%08x\n",
  1003. wdtr, clkp,
  1004. (u32)tcal.clocks.rdcc);
  1005. mfsdram(SDRAM_RTSR, val);
  1006. printf("** (%d)(%d) best "
  1007. "loop RTSR: 0x%08x\n",
  1008. wdtr, clkp, val);
  1009. mfsdram(SDRAM_FCSR, val);
  1010. printf("** (%d)(%d) best "
  1011. "loop FCSR: 0x%08x\n",
  1012. wdtr, clkp, val);
  1013. }
  1014. }
  1015. } /* if ((result != 0) && (val >= (ddr_rdss_opt()))) */
  1016. scan_list++;
  1017. } /* while ((scan_list->wrdtr != -1) && (scan_list->clktr != -1)) */
  1018. if (tcal.autocal.flags == 1) {
  1019. if (verbose_lvl > 0) {
  1020. printf("*** --------------\n");
  1021. printf("*** best_result window size: %d\n",
  1022. best_result);
  1023. printf("*** best_result WRDTR: 0x%04x\n",
  1024. tcal.clocks.wrdtr);
  1025. printf("*** best_result CLKTR: 0x%04x\n",
  1026. tcal.clocks.clktr);
  1027. printf("*** best_result RQFD: 0x%04x\n",
  1028. tcal.autocal.rqfd);
  1029. printf("*** best_result RFFD: 0x%04x\n",
  1030. tcal.autocal.rffd);
  1031. printf("*** best_result RDCC: 0x%04x\n",
  1032. tcal.clocks.rdcc);
  1033. printf("*** --------------\n");
  1034. printf("\n");
  1035. }
  1036. /*
  1037. * if got best passing result window, then lock in the
  1038. * best CLKTR, WRDTR, RQFD, and RFFD values
  1039. */
  1040. mfsdram(SDRAM_WRDTR, val);
  1041. mtsdram(SDRAM_WRDTR, (val &
  1042. ~(SDRAM_WRDTR_LLWP_MASK | SDRAM_WRDTR_WTR_MASK)) |
  1043. ddr_wrdtr(SDRAM_WRDTR_LLWP_1_CYC |
  1044. (tcal.clocks.wrdtr << 25)));
  1045. mtsdram(SDRAM_CLKTR, tcal.clocks.clktr << 30);
  1046. relock_memory_DLL();
  1047. mfsdram(SDRAM_RQDC, rqdc_reg);
  1048. rqdc_reg &= ~(SDRAM_RQDC_RQFD_MASK);
  1049. mtsdram(SDRAM_RQDC, rqdc_reg |
  1050. SDRAM_RQDC_RQFD_ENCODE(tcal.autocal.rqfd));
  1051. mfsdram(SDRAM_RQDC, rqdc_reg);
  1052. debug("*** best_result: read value SDRAM_RQDC 0x%08x\n",
  1053. rqdc_reg);
  1054. mfsdram(SDRAM_RFDC, rfdc_reg);
  1055. rfdc_reg &= ~(SDRAM_RFDC_RFFD_MASK);
  1056. mtsdram(SDRAM_RFDC, rfdc_reg |
  1057. SDRAM_RFDC_RFFD_ENCODE(tcal.autocal.rffd));
  1058. mfsdram(SDRAM_RFDC, rfdc_reg);
  1059. debug("*** best_result: read value SDRAM_RFDC 0x%08x\n",
  1060. rfdc_reg);
  1061. mfsdram(SDRAM_RDCC, val);
  1062. debug("*** SDRAM_RDCC 0x%08x\n", val);
  1063. } else {
  1064. /*
  1065. * no valid windows were found
  1066. */
  1067. printf("DQS memory calibration window can not be determined, "
  1068. "terminating u-boot.\n");
  1069. ppc4xx_ibm_ddr2_register_dump();
  1070. spd_ddr_init_hang();
  1071. }
  1072. blank_string(strlen(str));
  1073. return 0;
  1074. }
  1075. #else /* defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
  1076. u32 DQS_autocalibration(void)
  1077. {
  1078. return 0;
  1079. }
  1080. #endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */
  1081. #endif /* defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) */