ast_i2c.c 8.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2012-2020 ASPEED Technology Inc.
  4. * Copyright 2016 IBM Corporation
  5. * Copyright 2017 Google, Inc.
  6. */
  7. #include <common.h>
  8. #include <clk.h>
  9. #include <dm.h>
  10. #include <errno.h>
  11. #include <fdtdec.h>
  12. #include <i2c.h>
  13. #include <asm/io.h>
  14. #include <asm/arch/scu_ast2500.h>
  15. #include "ast_i2c.h"
  16. #define I2C_TIMEOUT_US 100000
  17. #define I2C_SLEEP_STEP_US 20
  18. #define HIGHSPEED_TTIMEOUT 3
  19. /*
  20. * Device private data
  21. */
  22. struct ast_i2c_priv {
  23. /* This device's clock */
  24. struct clk clk;
  25. /* Device registers */
  26. struct ast_i2c_regs *regs;
  27. /* I2C speed in Hz */
  28. int speed;
  29. };
  30. /*
  31. * Given desired divider ratio, return the value that needs to be set
  32. * in Clock and AC Timing Control register
  33. */
  34. static u32 get_clk_reg_val(ulong divider_ratio)
  35. {
  36. ulong inc = 0, div;
  37. ulong scl_low, scl_high, data;
  38. for (div = 0; divider_ratio >= 16; div++) {
  39. inc |= (divider_ratio & 1);
  40. divider_ratio >>= 1;
  41. }
  42. divider_ratio += inc;
  43. scl_low = (divider_ratio >> 1) - 1;
  44. scl_high = divider_ratio - scl_low - 2;
  45. data = I2CD_CACTC_BASE
  46. | (scl_high << I2CD_TCKHIGH_SHIFT)
  47. | (scl_low << I2CD_TCKLOW_SHIFT)
  48. | (div << I2CD_BASE_DIV_SHIFT);
  49. return data;
  50. }
  51. static void ast_i2c_clear_interrupts(struct udevice *dev)
  52. {
  53. struct ast_i2c_priv *priv = dev_get_priv(dev);
  54. writel(~0, &priv->regs->isr);
  55. }
  56. static void ast_i2c_init_bus(struct udevice *dev)
  57. {
  58. struct ast_i2c_priv *priv = dev_get_priv(dev);
  59. /* Reset device */
  60. writel(0, &priv->regs->fcr);
  61. /* Enable Master Mode. Assuming single-master */
  62. writel(I2CD_MASTER_EN
  63. | I2CD_M_SDA_LOCK_EN
  64. | I2CD_MULTI_MASTER_DIS | I2CD_M_SCL_DRIVE_EN,
  65. &priv->regs->fcr);
  66. /* Enable Interrupts */
  67. writel(I2CD_INTR_TX_ACK
  68. | I2CD_INTR_TX_NAK
  69. | I2CD_INTR_RX_DONE
  70. | I2CD_INTR_BUS_RECOVER_DONE
  71. | I2CD_INTR_NORMAL_STOP
  72. | I2CD_INTR_ABNORMAL, &priv->regs->icr);
  73. }
  74. static int ast_i2c_ofdata_to_platdata(struct udevice *dev)
  75. {
  76. struct ast_i2c_priv *priv = dev_get_priv(dev);
  77. int ret;
  78. priv->regs = devfdt_get_addr_ptr(dev);
  79. if (IS_ERR(priv->regs))
  80. return PTR_ERR(priv->regs);
  81. ret = clk_get_by_index(dev, 0, &priv->clk);
  82. if (ret < 0) {
  83. debug("%s: Can't get clock for %s: %d\n", __func__, dev->name,
  84. ret);
  85. return ret;
  86. }
  87. return 0;
  88. }
  89. static int ast_i2c_probe(struct udevice *dev)
  90. {
  91. struct ast2500_scu *scu;
  92. debug("Enabling I2C%u\n", dev->seq);
  93. /*
  94. * Get all I2C devices out of Reset.
  95. * Only needs to be done once, but doing it for every
  96. * device does not hurt.
  97. */
  98. scu = ast_get_scu();
  99. ast_scu_unlock(scu);
  100. clrbits_le32(&scu->sysreset_ctrl1, SCU_SYSRESET_I2C);
  101. ast_scu_lock(scu);
  102. ast_i2c_init_bus(dev);
  103. return 0;
  104. }
  105. static int ast_i2c_wait_isr(struct udevice *dev, u32 flag)
  106. {
  107. struct ast_i2c_priv *priv = dev_get_priv(dev);
  108. int timeout = I2C_TIMEOUT_US;
  109. while (!(readl(&priv->regs->isr) & flag) && timeout > 0) {
  110. udelay(I2C_SLEEP_STEP_US);
  111. timeout -= I2C_SLEEP_STEP_US;
  112. }
  113. ast_i2c_clear_interrupts(dev);
  114. if (timeout <= 0)
  115. return -ETIMEDOUT;
  116. return 0;
  117. }
  118. static int ast_i2c_send_stop(struct udevice *dev)
  119. {
  120. struct ast_i2c_priv *priv = dev_get_priv(dev);
  121. writel(I2CD_M_STOP_CMD, &priv->regs->csr);
  122. return ast_i2c_wait_isr(dev, I2CD_INTR_NORMAL_STOP);
  123. }
  124. static int ast_i2c_wait_tx(struct udevice *dev)
  125. {
  126. struct ast_i2c_priv *priv = dev_get_priv(dev);
  127. int timeout = I2C_TIMEOUT_US;
  128. u32 flag = I2CD_INTR_TX_ACK | I2CD_INTR_TX_NAK;
  129. u32 status = readl(&priv->regs->isr) & flag;
  130. int ret = 0;
  131. while (!status && timeout > 0) {
  132. status = readl(&priv->regs->isr) & flag;
  133. udelay(I2C_SLEEP_STEP_US);
  134. timeout -= I2C_SLEEP_STEP_US;
  135. }
  136. if (status == I2CD_INTR_TX_NAK)
  137. ret = -EREMOTEIO;
  138. if (timeout <= 0)
  139. ret = -ETIMEDOUT;
  140. ast_i2c_clear_interrupts(dev);
  141. return ret;
  142. }
  143. static int ast_i2c_start_txn(struct udevice *dev, uint devaddr)
  144. {
  145. struct ast_i2c_priv *priv = dev_get_priv(dev);
  146. /* Start and Send Device Address */
  147. writel(devaddr, &priv->regs->trbbr);
  148. writel(I2CD_M_START_CMD | I2CD_M_TX_CMD, &priv->regs->csr);
  149. return ast_i2c_wait_tx(dev);
  150. }
  151. static int ast_i2c_read_data(struct udevice *dev, u8 chip_addr, u8 *buffer,
  152. size_t len, bool send_stop)
  153. {
  154. struct ast_i2c_priv *priv = dev_get_priv(dev);
  155. u32 i2c_cmd = I2CD_M_RX_CMD;
  156. int ret;
  157. ret = ast_i2c_start_txn(dev, (chip_addr << 1) | I2C_M_RD);
  158. if (ret < 0)
  159. return ret;
  160. for (; len > 0; len--, buffer++) {
  161. if (len == 1)
  162. i2c_cmd |= I2CD_M_S_RX_CMD_LAST;
  163. writel(i2c_cmd, &priv->regs->csr);
  164. ret = ast_i2c_wait_isr(dev, I2CD_INTR_RX_DONE);
  165. if (ret < 0)
  166. return ret;
  167. *buffer = (readl(&priv->regs->trbbr) & I2CD_RX_DATA_MASK)
  168. >> I2CD_RX_DATA_SHIFT;
  169. }
  170. ast_i2c_clear_interrupts(dev);
  171. if (send_stop)
  172. return ast_i2c_send_stop(dev);
  173. return 0;
  174. }
  175. static int ast_i2c_write_data(struct udevice *dev, u8 chip_addr, u8
  176. *buffer, size_t len, bool send_stop)
  177. {
  178. struct ast_i2c_priv *priv = dev_get_priv(dev);
  179. int ret;
  180. ret = ast_i2c_start_txn(dev, (chip_addr << 1));
  181. if (ret < 0)
  182. return ret;
  183. for (; len > 0; len--, buffer++) {
  184. writel(*buffer, &priv->regs->trbbr);
  185. writel(I2CD_M_TX_CMD, &priv->regs->csr);
  186. ret = ast_i2c_wait_tx(dev);
  187. if (ret < 0)
  188. return ret;
  189. }
  190. if (send_stop)
  191. return ast_i2c_send_stop(dev);
  192. return 0;
  193. }
  194. static int ast_i2c_deblock(struct udevice *dev)
  195. {
  196. struct ast_i2c_priv *priv = dev_get_priv(dev);
  197. struct ast_i2c_regs *regs = priv->regs;
  198. u32 csr = readl(&regs->csr);
  199. bool sda_high = csr & I2CD_SDA_LINE_STS;
  200. bool scl_high = csr & I2CD_SCL_LINE_STS;
  201. int ret = 0;
  202. if (sda_high && scl_high) {
  203. /* Bus is idle, no deblocking needed. */
  204. return 0;
  205. } else if (sda_high) {
  206. /* Send stop command */
  207. debug("Unterminated TXN in (%x), sending stop\n", csr);
  208. ret = ast_i2c_send_stop(dev);
  209. } else if (scl_high) {
  210. /* Possibly stuck slave */
  211. debug("Bus stuck (%x), attempting recovery\n", csr);
  212. writel(I2CD_BUS_RECOVER_CMD, &regs->csr);
  213. ret = ast_i2c_wait_isr(dev, I2CD_INTR_BUS_RECOVER_DONE);
  214. } else {
  215. /* Just try to reinit the device. */
  216. ast_i2c_init_bus(dev);
  217. }
  218. return ret;
  219. }
  220. static int ast_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs)
  221. {
  222. int ret;
  223. ret = ast_i2c_deblock(dev);
  224. if (ret < 0)
  225. return ret;
  226. debug("i2c_xfer: %d messages\n", nmsgs);
  227. for (; nmsgs > 0; nmsgs--, msg++) {
  228. if (msg->flags & I2C_M_RD) {
  229. debug("i2c_read: chip=0x%x, len=0x%x, flags=0x%x\n",
  230. msg->addr, msg->len, msg->flags);
  231. ret = ast_i2c_read_data(dev, msg->addr, msg->buf,
  232. msg->len, (nmsgs == 1));
  233. } else {
  234. debug("i2c_write: chip=0x%x, len=0x%x, flags=0x%x\n",
  235. msg->addr, msg->len, msg->flags);
  236. ret = ast_i2c_write_data(dev, msg->addr, msg->buf,
  237. msg->len, (nmsgs == 1));
  238. }
  239. if (ret) {
  240. debug("%s: error (%d)\n", __func__, ret);
  241. return -EREMOTEIO;
  242. }
  243. }
  244. return 0;
  245. }
  246. static int ast_i2c_set_speed(struct udevice *dev, unsigned int speed)
  247. {
  248. struct ast_i2c_priv *priv = dev_get_priv(dev);
  249. struct ast_i2c_regs *regs = priv->regs;
  250. ulong i2c_rate, divider;
  251. debug("Setting speed for I2C%d to <%u>\n", dev->seq, speed);
  252. if (!speed) {
  253. debug("No valid speed specified\n");
  254. return -EINVAL;
  255. }
  256. i2c_rate = clk_get_rate(&priv->clk);
  257. divider = i2c_rate / speed;
  258. priv->speed = speed;
  259. if (speed > I2C_HIGHSPEED_RATE) {
  260. debug("Enable High Speed\n");
  261. setbits_le32(&regs->fcr, I2CD_M_HIGH_SPEED_EN
  262. | I2CD_M_SDA_DRIVE_1T_EN
  263. | I2CD_SDA_DRIVE_1T_EN);
  264. writel(HIGHSPEED_TTIMEOUT, &regs->cactcr2);
  265. } else {
  266. debug("Enabling Normal Speed\n");
  267. writel(I2CD_NO_TIMEOUT_CTRL, &regs->cactcr2);
  268. }
  269. writel(get_clk_reg_val(divider), &regs->cactcr1);
  270. ast_i2c_clear_interrupts(dev);
  271. return 0;
  272. }
  273. static const struct dm_i2c_ops ast_i2c_ops = {
  274. .xfer = ast_i2c_xfer,
  275. .set_bus_speed = ast_i2c_set_speed,
  276. .deblock = ast_i2c_deblock,
  277. };
  278. static const struct udevice_id ast_i2c_ids[] = {
  279. { .compatible = "aspeed,ast2400-i2c-bus" },
  280. { .compatible = "aspeed,ast2500-i2c-bus" },
  281. { },
  282. };
  283. U_BOOT_DRIVER(ast_i2c) = {
  284. .name = "ast_i2c",
  285. .id = UCLASS_I2C,
  286. .of_match = ast_i2c_ids,
  287. .probe = ast_i2c_probe,
  288. .ofdata_to_platdata = ast_i2c_ofdata_to_platdata,
  289. .priv_auto_alloc_size = sizeof(struct ast_i2c_priv),
  290. .ops = &ast_i2c_ops,
  291. };