cfi_flash.c 33 KB

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  1. /*
  2. * (C) Copyright 2002-2004
  3. * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com
  4. *
  5. * Copyright (C) 2003 Arabella Software Ltd.
  6. * Yuli Barcohen <yuli@arabellasw.com>
  7. * Modified to work with AMD flashes
  8. *
  9. * Copyright (C) 2004
  10. * Ed Okerson
  11. * Modified to work with little-endian systems.
  12. *
  13. * See file CREDITS for list of people who contributed to this
  14. * project.
  15. *
  16. * This program is free software; you can redistribute it and/or
  17. * modify it under the terms of the GNU General Public License as
  18. * published by the Free Software Foundation; either version 2 of
  19. * the License, or (at your option) any later version.
  20. *
  21. * This program is distributed in the hope that it will be useful,
  22. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  23. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  24. * GNU General Public License for more details.
  25. *
  26. * You should have received a copy of the GNU General Public License
  27. * along with this program; if not, write to the Free Software
  28. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  29. * MA 02111-1307 USA
  30. *
  31. * History
  32. * 01/20/2004 - combined variants of original driver.
  33. * 01/22/2004 - Write performance enhancements for parallel chips (Tolunay)
  34. * 01/23/2004 - Support for x8/x16 chips (Rune Raknerud)
  35. * 01/27/2004 - Little endian support Ed Okerson
  36. *
  37. * Tested Architectures
  38. * Port Width Chip Width # of banks Flash Chip Board
  39. * 32 16 1 28F128J3 seranoa/eagle
  40. * 64 16 1 28F128J3 seranoa/falcon
  41. *
  42. */
  43. /* The DEBUG define must be before common to enable debugging */
  44. /* #define DEBUG */
  45. #include <common.h>
  46. #include <asm/processor.h>
  47. #include <asm/byteorder.h>
  48. #include <linux/byteorder/swab.h>
  49. #ifdef CFG_FLASH_CFI_DRIVER
  50. /*
  51. * This file implements a Common Flash Interface (CFI) driver for U-Boot.
  52. * The width of the port and the width of the chips are determined at initialization.
  53. * These widths are used to calculate the address for access CFI data structures.
  54. * It has been tested on an Intel Strataflash implementation and AMD 29F016D.
  55. *
  56. * References
  57. * JEDEC Standard JESD68 - Common Flash Interface (CFI)
  58. * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes
  59. * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets
  60. * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet
  61. *
  62. * TODO
  63. *
  64. * Use Primary Extended Query table (PRI) and Alternate Algorithm Query
  65. * Table (ALT) to determine if protection is available
  66. *
  67. * Add support for other command sets Use the PRI and ALT to determine command set
  68. * Verify erase and program timeouts.
  69. */
  70. #ifndef CFG_FLASH_BANKS_LIST
  71. #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
  72. #endif
  73. #define FLASH_CMD_CFI 0x98
  74. #define FLASH_CMD_READ_ID 0x90
  75. #define FLASH_CMD_RESET 0xff
  76. #define FLASH_CMD_BLOCK_ERASE 0x20
  77. #define FLASH_CMD_ERASE_CONFIRM 0xD0
  78. #define FLASH_CMD_WRITE 0x40
  79. #define FLASH_CMD_PROTECT 0x60
  80. #define FLASH_CMD_PROTECT_SET 0x01
  81. #define FLASH_CMD_PROTECT_CLEAR 0xD0
  82. #define FLASH_CMD_CLEAR_STATUS 0x50
  83. #define FLASH_CMD_WRITE_TO_BUFFER 0xE8
  84. #define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0
  85. #define FLASH_STATUS_DONE 0x80
  86. #define FLASH_STATUS_ESS 0x40
  87. #define FLASH_STATUS_ECLBS 0x20
  88. #define FLASH_STATUS_PSLBS 0x10
  89. #define FLASH_STATUS_VPENS 0x08
  90. #define FLASH_STATUS_PSS 0x04
  91. #define FLASH_STATUS_DPS 0x02
  92. #define FLASH_STATUS_R 0x01
  93. #define FLASH_STATUS_PROTECT 0x01
  94. #define AMD_CMD_RESET 0xF0
  95. #define AMD_CMD_WRITE 0xA0
  96. #define AMD_CMD_ERASE_START 0x80
  97. #define AMD_CMD_ERASE_SECTOR 0x30
  98. #define AMD_CMD_UNLOCK_START 0xAA
  99. #define AMD_CMD_UNLOCK_ACK 0x55
  100. #define AMD_STATUS_TOGGLE 0x40
  101. #define AMD_STATUS_ERROR 0x20
  102. #define AMD_ADDR_ERASE_START 0x555
  103. #define AMD_ADDR_START 0x555
  104. #define AMD_ADDR_ACK 0x2AA
  105. #define FLASH_OFFSET_CFI 0x55
  106. #define FLASH_OFFSET_CFI_RESP 0x10
  107. #define FLASH_OFFSET_PRIMARY_VENDOR 0x13
  108. #define FLASH_OFFSET_WTOUT 0x1F
  109. #define FLASH_OFFSET_WBTOUT 0x20
  110. #define FLASH_OFFSET_ETOUT 0x21
  111. #define FLASH_OFFSET_CETOUT 0x22
  112. #define FLASH_OFFSET_WMAX_TOUT 0x23
  113. #define FLASH_OFFSET_WBMAX_TOUT 0x24
  114. #define FLASH_OFFSET_EMAX_TOUT 0x25
  115. #define FLASH_OFFSET_CEMAX_TOUT 0x26
  116. #define FLASH_OFFSET_SIZE 0x27
  117. #define FLASH_OFFSET_INTERFACE 0x28
  118. #define FLASH_OFFSET_BUFFER_SIZE 0x2A
  119. #define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C
  120. #define FLASH_OFFSET_ERASE_REGIONS 0x2D
  121. #define FLASH_OFFSET_PROTECT 0x02
  122. #define FLASH_OFFSET_USER_PROTECTION 0x85
  123. #define FLASH_OFFSET_INTEL_PROTECTION 0x81
  124. #define FLASH_MAN_CFI 0x01000000
  125. #define CFI_CMDSET_NONE 0
  126. #define CFI_CMDSET_INTEL_EXTENDED 1
  127. #define CFI_CMDSET_AMD_STANDARD 2
  128. #define CFI_CMDSET_INTEL_STANDARD 3
  129. #define CFI_CMDSET_AMD_EXTENDED 4
  130. #define CFI_CMDSET_MITSU_STANDARD 256
  131. #define CFI_CMDSET_MITSU_EXTENDED 257
  132. #define CFI_CMDSET_SST 258
  133. typedef union {
  134. unsigned char c;
  135. unsigned short w;
  136. unsigned long l;
  137. unsigned long long ll;
  138. } cfiword_t;
  139. typedef union {
  140. volatile unsigned char *cp;
  141. volatile unsigned short *wp;
  142. volatile unsigned long *lp;
  143. volatile unsigned long long *llp;
  144. } cfiptr_t;
  145. #define NUM_ERASE_REGIONS 4
  146. static ulong bank_base[CFG_MAX_FLASH_BANKS] = CFG_FLASH_BANKS_LIST;
  147. flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
  148. /*-----------------------------------------------------------------------
  149. * Functions
  150. */
  151. typedef unsigned long flash_sect_t;
  152. static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c);
  153. static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf);
  154. static void flash_write_cmd (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd);
  155. static void flash_unlock_seq (flash_info_t * info, flash_sect_t sect);
  156. static int flash_isequal (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd);
  157. static int flash_isset (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd);
  158. static int flash_toggle (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd);
  159. static int flash_detect_cfi (flash_info_t * info);
  160. static ulong flash_get_size (ulong base, int banknum);
  161. static int flash_write_cfiword (flash_info_t * info, ulong dest, cfiword_t cword);
  162. static int flash_full_status_check (flash_info_t * info, flash_sect_t sector,
  163. ulong tout, char *prompt);
  164. #ifdef CFG_FLASH_USE_BUFFER_WRITE
  165. static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp, int len);
  166. #endif
  167. /*-----------------------------------------------------------------------
  168. * create an address based on the offset and the port width
  169. */
  170. inline uchar *flash_make_addr (flash_info_t * info, flash_sect_t sect, uint offset)
  171. {
  172. return ((uchar *) (info->start[sect] + (offset * info->portwidth)));
  173. }
  174. #ifdef DEBUG
  175. /*-----------------------------------------------------------------------
  176. * Debug support
  177. */
  178. void print_longlong (char *str, unsigned long long data)
  179. {
  180. int i;
  181. char *cp;
  182. cp = (unsigned char *) &data;
  183. for (i = 0; i < 8; i++)
  184. sprintf (&str[i * 2], "%2.2x", *cp++);
  185. }
  186. static void flash_printqry (flash_info_t * info, flash_sect_t sect)
  187. {
  188. cfiptr_t cptr;
  189. int x, y;
  190. for (x = 0; x < 0x40; x += 16 / info->portwidth) {
  191. cptr.cp =
  192. flash_make_addr (info, sect,
  193. x + FLASH_OFFSET_CFI_RESP);
  194. debug ("%p : ", cptr.cp);
  195. for (y = 0; y < 16; y++) {
  196. debug ("%2.2x ", cptr.cp[y]);
  197. }
  198. debug (" ");
  199. for (y = 0; y < 16; y++) {
  200. if (cptr.cp[y] >= 0x20 && cptr.cp[y] <= 0x7e) {
  201. debug ("%c", cptr.cp[y]);
  202. } else {
  203. debug (".");
  204. }
  205. }
  206. debug ("\n");
  207. }
  208. }
  209. #endif
  210. /*-----------------------------------------------------------------------
  211. * read a character at a port width address
  212. */
  213. inline uchar flash_read_uchar (flash_info_t * info, uint offset)
  214. {
  215. uchar *cp;
  216. cp = flash_make_addr (info, 0, offset);
  217. #if defined(__LITTLE_ENDIAN)
  218. return (cp[0]);
  219. #else
  220. return (cp[info->portwidth - 1]);
  221. #endif
  222. }
  223. /*-----------------------------------------------------------------------
  224. * read a short word by swapping for ppc format.
  225. */
  226. ushort flash_read_ushort (flash_info_t * info, flash_sect_t sect, uint offset)
  227. {
  228. uchar *addr;
  229. ushort retval;
  230. #ifdef DEBUG
  231. int x;
  232. #endif
  233. addr = flash_make_addr (info, sect, offset);
  234. #ifdef DEBUG
  235. debug ("ushort addr is at %p info->portwidth = %d\n", addr,
  236. info->portwidth);
  237. for (x = 0; x < 2 * info->portwidth; x++) {
  238. debug ("addr[%x] = 0x%x\n", x, addr[x]);
  239. }
  240. #endif
  241. #if defined(__LITTLE_ENDIAN)
  242. retval = ((addr[(info->portwidth)] << 8) | addr[0]);
  243. #else
  244. retval = ((addr[(2 * info->portwidth) - 1] << 8) |
  245. addr[info->portwidth - 1]);
  246. #endif
  247. debug ("retval = 0x%x\n", retval);
  248. return retval;
  249. }
  250. /*-----------------------------------------------------------------------
  251. * read a long word by picking the least significant byte of each maiximum
  252. * port size word. Swap for ppc format.
  253. */
  254. ulong flash_read_long (flash_info_t * info, flash_sect_t sect, uint offset)
  255. {
  256. uchar *addr;
  257. ulong retval;
  258. #ifdef DEBUG
  259. int x;
  260. #endif
  261. addr = flash_make_addr (info, sect, offset);
  262. #ifdef DEBUG
  263. debug ("long addr is at %p info->portwidth = %d\n", addr,
  264. info->portwidth);
  265. for (x = 0; x < 4 * info->portwidth; x++) {
  266. debug ("addr[%x] = 0x%x\n", x, addr[x]);
  267. }
  268. #endif
  269. #if defined(__LITTLE_ENDIAN)
  270. retval = (addr[0] << 16) | (addr[(info->portwidth)] << 24) |
  271. (addr[(2 * info->portwidth)]) | (addr[(3 * info->portwidth)] << 8);
  272. #else
  273. retval = (addr[(2 * info->portwidth) - 1] << 24) |
  274. (addr[(info->portwidth) - 1] << 16) |
  275. (addr[(4 * info->portwidth) - 1] << 8) |
  276. addr[(3 * info->portwidth) - 1];
  277. #endif
  278. return retval;
  279. }
  280. /*-----------------------------------------------------------------------
  281. */
  282. unsigned long flash_init (void)
  283. {
  284. unsigned long size = 0;
  285. int i;
  286. /* Init: no FLASHes known */
  287. for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
  288. flash_info[i].flash_id = FLASH_UNKNOWN;
  289. size += flash_info[i].size = flash_get_size (bank_base[i], i);
  290. if (flash_info[i].flash_id == FLASH_UNKNOWN) {
  291. printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
  292. i, flash_info[i].size, flash_info[i].size << 20);
  293. }
  294. }
  295. /* Monitor protection ON by default */
  296. #if (CFG_MONITOR_BASE >= CFG_FLASH_BASE)
  297. flash_protect (FLAG_PROTECT_SET,
  298. CFG_MONITOR_BASE,
  299. CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
  300. &flash_info[0]);
  301. #endif
  302. /* Environment protection ON by default */
  303. #ifdef CFG_ENV_IS_IN_FLASH
  304. flash_protect (FLAG_PROTECT_SET,
  305. CFG_ENV_ADDR,
  306. CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
  307. &flash_info[0]);
  308. #endif
  309. /* Redundant environment protection ON by default */
  310. #ifdef CFG_ENV_ADDR_REDUND
  311. flash_protect (FLAG_PROTECT_SET,
  312. CFG_ENV_ADDR_REDUND,
  313. CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1,
  314. &flash_info[0]);
  315. #endif
  316. return (size);
  317. }
  318. /*-----------------------------------------------------------------------
  319. */
  320. int flash_erase (flash_info_t * info, int s_first, int s_last)
  321. {
  322. int rcode = 0;
  323. int prot;
  324. flash_sect_t sect;
  325. if (info->flash_id != FLASH_MAN_CFI) {
  326. puts ("Can't erase unknown flash type - aborted\n");
  327. return 1;
  328. }
  329. if ((s_first < 0) || (s_first > s_last)) {
  330. puts ("- no sectors to erase\n");
  331. return 1;
  332. }
  333. prot = 0;
  334. for (sect = s_first; sect <= s_last; ++sect) {
  335. if (info->protect[sect]) {
  336. prot++;
  337. }
  338. }
  339. if (prot) {
  340. printf ("- Warning: %d protected sectors will not be erased!\n", prot);
  341. } else {
  342. putc ('\n');
  343. }
  344. for (sect = s_first; sect <= s_last; sect++) {
  345. if (info->protect[sect] == 0) { /* not protected */
  346. switch (info->vendor) {
  347. case CFI_CMDSET_INTEL_STANDARD:
  348. case CFI_CMDSET_INTEL_EXTENDED:
  349. flash_write_cmd (info, sect, 0, FLASH_CMD_CLEAR_STATUS);
  350. flash_write_cmd (info, sect, 0, FLASH_CMD_BLOCK_ERASE);
  351. flash_write_cmd (info, sect, 0, FLASH_CMD_ERASE_CONFIRM);
  352. break;
  353. case CFI_CMDSET_AMD_STANDARD:
  354. case CFI_CMDSET_AMD_EXTENDED:
  355. flash_unlock_seq (info, sect);
  356. flash_write_cmd (info, sect, AMD_ADDR_ERASE_START,
  357. AMD_CMD_ERASE_START);
  358. flash_unlock_seq (info, sect);
  359. flash_write_cmd (info, sect, 0, AMD_CMD_ERASE_SECTOR);
  360. break;
  361. default:
  362. debug ("Unkown flash vendor %d\n",
  363. info->vendor);
  364. break;
  365. }
  366. if (flash_full_status_check
  367. (info, sect, info->erase_blk_tout, "erase")) {
  368. rcode = 1;
  369. } else
  370. putc ('.');
  371. }
  372. }
  373. puts (" done\n");
  374. return rcode;
  375. }
  376. /*-----------------------------------------------------------------------
  377. */
  378. void flash_print_info (flash_info_t * info)
  379. {
  380. int i;
  381. if (info->flash_id != FLASH_MAN_CFI) {
  382. puts ("missing or unknown FLASH type\n");
  383. return;
  384. }
  385. printf ("CFI conformant FLASH (%d x %d)",
  386. (info->portwidth << 3), (info->chipwidth << 3));
  387. printf (" Size: %ld MB in %d Sectors\n",
  388. info->size >> 20, info->sector_count);
  389. printf (" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n",
  390. info->erase_blk_tout,
  391. info->write_tout,
  392. info->buffer_write_tout,
  393. info->buffer_size);
  394. puts (" Sector Start Addresses:");
  395. for (i = 0; i < info->sector_count; ++i) {
  396. #ifdef CFG_FLASH_EMPTY_INFO
  397. int k;
  398. int size;
  399. int erased;
  400. volatile unsigned long *flash;
  401. /*
  402. * Check if whole sector is erased
  403. */
  404. if (i != (info->sector_count - 1))
  405. size = info->start[i + 1] - info->start[i];
  406. else
  407. size = info->start[0] + info->size - info->start[i];
  408. erased = 1;
  409. flash = (volatile unsigned long *) info->start[i];
  410. size = size >> 2; /* divide by 4 for longword access */
  411. for (k = 0; k < size; k++) {
  412. if (*flash++ != 0xffffffff) {
  413. erased = 0;
  414. break;
  415. }
  416. }
  417. if ((i % 5) == 0)
  418. printf ("\n");
  419. /* print empty and read-only info */
  420. printf (" %08lX%s%s",
  421. info->start[i],
  422. erased ? " E" : " ",
  423. info->protect[i] ? "RO " : " ");
  424. #else
  425. if ((i % 5) == 0)
  426. printf ("\n ");
  427. printf (" %08lX%s",
  428. info->start[i], info->protect[i] ? " (RO) " : " ");
  429. #endif
  430. }
  431. putc ('\n');
  432. return;
  433. }
  434. /*-----------------------------------------------------------------------
  435. * Copy memory to flash, returns:
  436. * 0 - OK
  437. * 1 - write timeout
  438. * 2 - Flash not erased
  439. */
  440. int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
  441. {
  442. ulong wp;
  443. ulong cp;
  444. int aln;
  445. cfiword_t cword;
  446. int i, rc;
  447. #ifdef CFG_FLASH_USE_BUFFER_WRITE
  448. int buffered_size;
  449. #endif
  450. /* get lower aligned address */
  451. /* get lower aligned address */
  452. wp = (addr & ~(info->portwidth - 1));
  453. /* handle unaligned start */
  454. if ((aln = addr - wp) != 0) {
  455. cword.l = 0;
  456. cp = wp;
  457. for (i = 0; i < aln; ++i, ++cp)
  458. flash_add_byte (info, &cword, (*(uchar *) cp));
  459. for (; (i < info->portwidth) && (cnt > 0); i++) {
  460. flash_add_byte (info, &cword, *src++);
  461. cnt--;
  462. cp++;
  463. }
  464. for (; (cnt == 0) && (i < info->portwidth); ++i, ++cp)
  465. flash_add_byte (info, &cword, (*(uchar *) cp));
  466. if ((rc = flash_write_cfiword (info, wp, cword)) != 0)
  467. return rc;
  468. wp = cp;
  469. }
  470. /* handle the aligned part */
  471. #ifdef CFG_FLASH_USE_BUFFER_WRITE
  472. buffered_size = (info->portwidth / info->chipwidth);
  473. buffered_size *= info->buffer_size;
  474. while (cnt >= info->portwidth) {
  475. i = buffered_size > cnt ? cnt : buffered_size;
  476. if ((rc = flash_write_cfibuffer (info, wp, src, i)) != ERR_OK)
  477. return rc;
  478. i -= (i % info->portwidth);
  479. wp += i;
  480. src += i;
  481. cnt -= i;
  482. }
  483. #else
  484. while (cnt >= info->portwidth) {
  485. cword.l = 0;
  486. for (i = 0; i < info->portwidth; i++) {
  487. flash_add_byte (info, &cword, *src++);
  488. }
  489. if ((rc = flash_write_cfiword (info, wp, cword)) != 0)
  490. return rc;
  491. wp += info->portwidth;
  492. cnt -= info->portwidth;
  493. }
  494. #endif /* CFG_FLASH_USE_BUFFER_WRITE */
  495. if (cnt == 0) {
  496. return (0);
  497. }
  498. /*
  499. * handle unaligned tail bytes
  500. */
  501. cword.l = 0;
  502. for (i = 0, cp = wp; (i < info->portwidth) && (cnt > 0); ++i, ++cp) {
  503. flash_add_byte (info, &cword, *src++);
  504. --cnt;
  505. }
  506. for (; i < info->portwidth; ++i, ++cp) {
  507. flash_add_byte (info, &cword, (*(uchar *) cp));
  508. }
  509. return flash_write_cfiword (info, wp, cword);
  510. }
  511. /*-----------------------------------------------------------------------
  512. */
  513. #ifdef CFG_FLASH_PROTECTION
  514. int flash_real_protect (flash_info_t * info, long sector, int prot)
  515. {
  516. int retcode = 0;
  517. flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
  518. flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT);
  519. if (prot)
  520. flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_SET);
  521. else
  522. flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_CLEAR);
  523. if ((retcode =
  524. flash_full_status_check (info, sector, info->erase_blk_tout,
  525. prot ? "protect" : "unprotect")) == 0) {
  526. info->protect[sector] = prot;
  527. /* Intel's unprotect unprotects all locking */
  528. if (prot == 0) {
  529. flash_sect_t i;
  530. for (i = 0; i < info->sector_count; i++) {
  531. if (info->protect[i])
  532. flash_real_protect (info, i, 1);
  533. }
  534. }
  535. }
  536. return retcode;
  537. }
  538. /*-----------------------------------------------------------------------
  539. * flash_read_user_serial - read the OneTimeProgramming cells
  540. */
  541. void flash_read_user_serial (flash_info_t * info, void *buffer, int offset,
  542. int len)
  543. {
  544. uchar *src;
  545. uchar *dst;
  546. dst = buffer;
  547. src = flash_make_addr (info, 0, FLASH_OFFSET_USER_PROTECTION);
  548. flash_write_cmd (info, 0, 0, FLASH_CMD_READ_ID);
  549. memcpy (dst, src + offset, len);
  550. flash_write_cmd (info, 0, 0, FLASH_CMD_RESET);
  551. }
  552. /*
  553. * flash_read_factory_serial - read the device Id from the protection area
  554. */
  555. void flash_read_factory_serial (flash_info_t * info, void *buffer, int offset,
  556. int len)
  557. {
  558. uchar *src;
  559. src = flash_make_addr (info, 0, FLASH_OFFSET_INTEL_PROTECTION);
  560. flash_write_cmd (info, 0, 0, FLASH_CMD_READ_ID);
  561. memcpy (buffer, src + offset, len);
  562. flash_write_cmd (info, 0, 0, FLASH_CMD_RESET);
  563. }
  564. #endif /* CFG_FLASH_PROTECTION */
  565. /*
  566. * flash_is_busy - check to see if the flash is busy
  567. * This routine checks the status of the chip and returns true if the chip is busy
  568. */
  569. static int flash_is_busy (flash_info_t * info, flash_sect_t sect)
  570. {
  571. int retval;
  572. switch (info->vendor) {
  573. case CFI_CMDSET_INTEL_STANDARD:
  574. case CFI_CMDSET_INTEL_EXTENDED:
  575. retval = !flash_isset (info, sect, 0, FLASH_STATUS_DONE);
  576. break;
  577. case CFI_CMDSET_AMD_STANDARD:
  578. case CFI_CMDSET_AMD_EXTENDED:
  579. retval = flash_toggle (info, sect, 0, AMD_STATUS_TOGGLE);
  580. break;
  581. default:
  582. retval = 0;
  583. }
  584. debug ("flash_is_busy: %d\n", retval);
  585. return retval;
  586. }
  587. /*-----------------------------------------------------------------------
  588. * wait for XSR.7 to be set. Time out with an error if it does not.
  589. * This routine does not set the flash to read-array mode.
  590. */
  591. static int flash_status_check (flash_info_t * info, flash_sect_t sector,
  592. ulong tout, char *prompt)
  593. {
  594. ulong start;
  595. /* Wait for command completion */
  596. start = get_timer (0);
  597. while (flash_is_busy (info, sector)) {
  598. if (get_timer (start) > info->erase_blk_tout * CFG_HZ) {
  599. printf ("Flash %s timeout at address %lx data %lx\n",
  600. prompt, info->start[sector],
  601. flash_read_long (info, sector, 0));
  602. flash_write_cmd (info, sector, 0, info->cmd_reset);
  603. return ERR_TIMOUT;
  604. }
  605. }
  606. return ERR_OK;
  607. }
  608. /*-----------------------------------------------------------------------
  609. * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check.
  610. * This routine sets the flash to read-array mode.
  611. */
  612. static int flash_full_status_check (flash_info_t * info, flash_sect_t sector,
  613. ulong tout, char *prompt)
  614. {
  615. int retcode;
  616. retcode = flash_status_check (info, sector, tout, prompt);
  617. switch (info->vendor) {
  618. case CFI_CMDSET_INTEL_EXTENDED:
  619. case CFI_CMDSET_INTEL_STANDARD:
  620. if ((retcode != ERR_OK)
  621. && !flash_isequal (info, sector, 0, FLASH_STATUS_DONE)) {
  622. retcode = ERR_INVAL;
  623. printf ("Flash %s error at address %lx\n", prompt,
  624. info->start[sector]);
  625. if (flash_isset (info, sector, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)) {
  626. puts ("Command Sequence Error.\n");
  627. } else if (flash_isset (info, sector, 0, FLASH_STATUS_ECLBS)) {
  628. puts ("Block Erase Error.\n");
  629. retcode = ERR_NOT_ERASED;
  630. } else if (flash_isset (info, sector, 0, FLASH_STATUS_PSLBS)) {
  631. puts ("Locking Error\n");
  632. }
  633. if (flash_isset (info, sector, 0, FLASH_STATUS_DPS)) {
  634. puts ("Block locked.\n");
  635. retcode = ERR_PROTECTED;
  636. }
  637. if (flash_isset (info, sector, 0, FLASH_STATUS_VPENS))
  638. puts ("Vpp Low Error.\n");
  639. }
  640. flash_write_cmd (info, sector, 0, FLASH_CMD_RESET);
  641. break;
  642. default:
  643. break;
  644. }
  645. return retcode;
  646. }
  647. /*-----------------------------------------------------------------------
  648. */
  649. static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c)
  650. {
  651. #if defined(__LITTLE_ENDIAN)
  652. unsigned short w;
  653. unsigned int l;
  654. unsigned long long ll;
  655. #endif
  656. switch (info->portwidth) {
  657. case FLASH_CFI_8BIT:
  658. cword->c = c;
  659. break;
  660. case FLASH_CFI_16BIT:
  661. #if defined(__LITTLE_ENDIAN)
  662. w = c;
  663. w <<= 8;
  664. cword->w = (cword->w >> 8) | w;
  665. #else
  666. cword->w = (cword->w << 8) | c;
  667. #endif
  668. break;
  669. case FLASH_CFI_32BIT:
  670. #if defined(__LITTLE_ENDIAN)
  671. l = c;
  672. l <<= 24;
  673. cword->l = (cword->l >> 8) | l;
  674. #else
  675. cword->l = (cword->l << 8) | c;
  676. #endif
  677. break;
  678. case FLASH_CFI_64BIT:
  679. #if defined(__LITTLE_ENDIAN)
  680. ll = c;
  681. ll <<= 56;
  682. cword->ll = (cword->ll >> 8) | ll;
  683. #else
  684. cword->ll = (cword->ll << 8) | c;
  685. #endif
  686. break;
  687. }
  688. }
  689. /*-----------------------------------------------------------------------
  690. * make a proper sized command based on the port and chip widths
  691. */
  692. static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf)
  693. {
  694. int i;
  695. #if defined(__LITTLE_ENDIAN)
  696. ushort stmpw;
  697. uint stmpi;
  698. #endif
  699. uchar *cp = (uchar *) cmdbuf;
  700. for (i = 0; i < info->portwidth; i++)
  701. *cp++ = ((i + 1) % info->chipwidth) ? '\0' : cmd;
  702. #if defined(__LITTLE_ENDIAN)
  703. switch (info->portwidth) {
  704. case FLASH_CFI_8BIT:
  705. break;
  706. case FLASH_CFI_16BIT:
  707. stmpw = *(ushort *) cmdbuf;
  708. *(ushort *) cmdbuf = __swab16 (stmpw);
  709. break;
  710. case FLASH_CFI_32BIT:
  711. stmpi = *(uint *) cmdbuf;
  712. *(uint *) cmdbuf = __swab32 (stmpi);
  713. break;
  714. default:
  715. puts ("WARNING: flash_make_cmd: unsuppported LittleEndian mode\n");
  716. break;
  717. }
  718. #endif
  719. }
  720. /*
  721. * Write a proper sized command to the correct address
  722. */
  723. static void flash_write_cmd (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd)
  724. {
  725. volatile cfiptr_t addr;
  726. cfiword_t cword;
  727. addr.cp = flash_make_addr (info, sect, offset);
  728. flash_make_cmd (info, cmd, &cword);
  729. switch (info->portwidth) {
  730. case FLASH_CFI_8BIT:
  731. debug ("fwc addr %p cmd %x %x 8bit x %d bit\n", addr.cp, cmd,
  732. cword.c, info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
  733. *addr.cp = cword.c;
  734. break;
  735. case FLASH_CFI_16BIT:
  736. debug ("fwc addr %p cmd %x %4.4x 16bit x %d bit\n", addr.wp,
  737. cmd, cword.w,
  738. info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
  739. *addr.wp = cword.w;
  740. break;
  741. case FLASH_CFI_32BIT:
  742. debug ("fwc addr %p cmd %x %8.8lx 32bit x %d bit\n", addr.lp,
  743. cmd, cword.l,
  744. info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
  745. *addr.lp = cword.l;
  746. break;
  747. case FLASH_CFI_64BIT:
  748. #ifdef DEBUG
  749. {
  750. char str[20];
  751. print_longlong (str, cword.ll);
  752. debug ("fwrite addr %p cmd %x %s 64 bit x %d bit\n",
  753. addr.llp, cmd, str,
  754. info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
  755. }
  756. #endif
  757. *addr.llp = cword.ll;
  758. break;
  759. }
  760. }
  761. static void flash_unlock_seq (flash_info_t * info, flash_sect_t sect)
  762. {
  763. flash_write_cmd (info, sect, AMD_ADDR_START, AMD_CMD_UNLOCK_START);
  764. flash_write_cmd (info, sect, AMD_ADDR_ACK, AMD_CMD_UNLOCK_ACK);
  765. }
  766. /*-----------------------------------------------------------------------
  767. */
  768. static int flash_isequal (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd)
  769. {
  770. cfiptr_t cptr;
  771. cfiword_t cword;
  772. int retval;
  773. cptr.cp = flash_make_addr (info, sect, offset);
  774. flash_make_cmd (info, cmd, &cword);
  775. debug ("is= cmd %x(%c) addr %p ", cmd, cmd, cptr.cp);
  776. switch (info->portwidth) {
  777. case FLASH_CFI_8BIT:
  778. debug ("is= %x %x\n", cptr.cp[0], cword.c);
  779. retval = (cptr.cp[0] == cword.c);
  780. break;
  781. case FLASH_CFI_16BIT:
  782. debug ("is= %4.4x %4.4x\n", cptr.wp[0], cword.w);
  783. retval = (cptr.wp[0] == cword.w);
  784. break;
  785. case FLASH_CFI_32BIT:
  786. debug ("is= %8.8lx %8.8lx\n", cptr.lp[0], cword.l);
  787. retval = (cptr.lp[0] == cword.l);
  788. break;
  789. case FLASH_CFI_64BIT:
  790. #ifdef DEBUG
  791. {
  792. char str1[20];
  793. char str2[20];
  794. print_longlong (str1, cptr.llp[0]);
  795. print_longlong (str2, cword.ll);
  796. debug ("is= %s %s\n", str1, str2);
  797. }
  798. #endif
  799. retval = (cptr.llp[0] == cword.ll);
  800. break;
  801. default:
  802. retval = 0;
  803. break;
  804. }
  805. return retval;
  806. }
  807. /*-----------------------------------------------------------------------
  808. */
  809. static int flash_isset (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd)
  810. {
  811. cfiptr_t cptr;
  812. cfiword_t cword;
  813. int retval;
  814. cptr.cp = flash_make_addr (info, sect, offset);
  815. flash_make_cmd (info, cmd, &cword);
  816. switch (info->portwidth) {
  817. case FLASH_CFI_8BIT:
  818. retval = ((cptr.cp[0] & cword.c) == cword.c);
  819. break;
  820. case FLASH_CFI_16BIT:
  821. retval = ((cptr.wp[0] & cword.w) == cword.w);
  822. break;
  823. case FLASH_CFI_32BIT:
  824. retval = ((cptr.lp[0] & cword.l) == cword.l);
  825. break;
  826. case FLASH_CFI_64BIT:
  827. retval = ((cptr.llp[0] & cword.ll) == cword.ll);
  828. break;
  829. default:
  830. retval = 0;
  831. break;
  832. }
  833. return retval;
  834. }
  835. /*-----------------------------------------------------------------------
  836. */
  837. static int flash_toggle (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd)
  838. {
  839. cfiptr_t cptr;
  840. cfiword_t cword;
  841. int retval;
  842. cptr.cp = flash_make_addr (info, sect, offset);
  843. flash_make_cmd (info, cmd, &cword);
  844. switch (info->portwidth) {
  845. case FLASH_CFI_8BIT:
  846. retval = ((cptr.cp[0] & cword.c) != (cptr.cp[0] & cword.c));
  847. break;
  848. case FLASH_CFI_16BIT:
  849. retval = ((cptr.wp[0] & cword.w) != (cptr.wp[0] & cword.w));
  850. break;
  851. case FLASH_CFI_32BIT:
  852. retval = ((cptr.lp[0] & cword.l) != (cptr.lp[0] & cword.l));
  853. break;
  854. case FLASH_CFI_64BIT:
  855. retval = ((cptr.llp[0] & cword.ll) !=
  856. (cptr.llp[0] & cword.ll));
  857. break;
  858. default:
  859. retval = 0;
  860. break;
  861. }
  862. return retval;
  863. }
  864. /*-----------------------------------------------------------------------
  865. * detect if flash is compatible with the Common Flash Interface (CFI)
  866. * http://www.jedec.org/download/search/jesd68.pdf
  867. *
  868. */
  869. static int flash_detect_cfi (flash_info_t * info)
  870. {
  871. debug ("flash detect cfi\n");
  872. for (info->portwidth = FLASH_CFI_8BIT;
  873. info->portwidth <= FLASH_CFI_64BIT; info->portwidth <<= 1) {
  874. for (info->chipwidth = FLASH_CFI_BY8;
  875. info->chipwidth <= info->portwidth;
  876. info->chipwidth <<= 1) {
  877. flash_write_cmd (info, 0, 0, FLASH_CMD_RESET);
  878. flash_write_cmd (info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI);
  879. if (flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP, 'Q')
  880. && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R')
  881. && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) {
  882. info->interface = flash_read_ushort (info, 0, FLASH_OFFSET_INTERFACE);
  883. debug ("device interface is %d\n",
  884. info->interface);
  885. debug ("found port %d chip %d ",
  886. info->portwidth, info->chipwidth);
  887. debug ("port %d bits chip %d bits\n",
  888. info->portwidth << CFI_FLASH_SHIFT_WIDTH,
  889. info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
  890. return 1;
  891. }
  892. }
  893. }
  894. debug ("not found\n");
  895. return 0;
  896. }
  897. /*
  898. * The following code cannot be run from FLASH!
  899. *
  900. */
  901. static ulong flash_get_size (ulong base, int banknum)
  902. {
  903. flash_info_t *info = &flash_info[banknum];
  904. int i, j;
  905. flash_sect_t sect_cnt;
  906. unsigned long sector;
  907. unsigned long tmp;
  908. int size_ratio;
  909. uchar num_erase_regions;
  910. int erase_region_size;
  911. int erase_region_count;
  912. info->start[0] = base;
  913. if (flash_detect_cfi (info)) {
  914. info->vendor = flash_read_ushort (info, 0, FLASH_OFFSET_PRIMARY_VENDOR);
  915. #ifdef DEBUG
  916. flash_printqry (info, 0);
  917. #endif
  918. switch (info->vendor) {
  919. case CFI_CMDSET_INTEL_STANDARD:
  920. case CFI_CMDSET_INTEL_EXTENDED:
  921. default:
  922. info->cmd_reset = FLASH_CMD_RESET;
  923. break;
  924. case CFI_CMDSET_AMD_STANDARD:
  925. case CFI_CMDSET_AMD_EXTENDED:
  926. info->cmd_reset = AMD_CMD_RESET;
  927. break;
  928. }
  929. debug ("manufacturer is %d\n", info->vendor);
  930. size_ratio = info->portwidth / info->chipwidth;
  931. /* if the chip is x8/x16 reduce the ratio by half */
  932. if ((info->interface == FLASH_CFI_X8X16)
  933. && (info->chipwidth == FLASH_CFI_BY8)) {
  934. size_ratio >>= 1;
  935. }
  936. num_erase_regions = flash_read_uchar (info, FLASH_OFFSET_NUM_ERASE_REGIONS);
  937. debug ("size_ratio %d port %d bits chip %d bits\n",
  938. size_ratio, info->portwidth << CFI_FLASH_SHIFT_WIDTH,
  939. info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
  940. debug ("found %d erase regions\n", num_erase_regions);
  941. sect_cnt = 0;
  942. sector = base;
  943. for (i = 0; i < num_erase_regions; i++) {
  944. if (i > NUM_ERASE_REGIONS) {
  945. printf ("%d erase regions found, only %d used\n",
  946. num_erase_regions, NUM_ERASE_REGIONS);
  947. break;
  948. }
  949. tmp = flash_read_long (info, 0,
  950. FLASH_OFFSET_ERASE_REGIONS +
  951. i * 4);
  952. erase_region_size =
  953. (tmp & 0xffff) ? ((tmp & 0xffff) * 256) : 128;
  954. tmp >>= 16;
  955. erase_region_count = (tmp & 0xffff) + 1;
  956. debug ("erase_region_count = %d erase_region_size = %d\n",
  957. erase_region_count, erase_region_size);
  958. for (j = 0; j < erase_region_count; j++) {
  959. info->start[sect_cnt] = sector;
  960. sector += (erase_region_size * size_ratio);
  961. info->protect[sect_cnt] =
  962. flash_isset (info, sect_cnt,
  963. FLASH_OFFSET_PROTECT,
  964. FLASH_STATUS_PROTECT);
  965. sect_cnt++;
  966. }
  967. }
  968. info->sector_count = sect_cnt;
  969. /* multiply the size by the number of chips */
  970. info->size = (1 << flash_read_uchar (info, FLASH_OFFSET_SIZE)) * size_ratio;
  971. info->buffer_size = (1 << flash_read_ushort (info, 0, FLASH_OFFSET_BUFFER_SIZE));
  972. tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_ETOUT);
  973. info->erase_blk_tout = (tmp * (1 << flash_read_uchar (info, FLASH_OFFSET_EMAX_TOUT)));
  974. tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_WBTOUT);
  975. info->buffer_write_tout = (tmp * (1 << flash_read_uchar (info, FLASH_OFFSET_WBMAX_TOUT)));
  976. tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_WTOUT);
  977. info->write_tout = (tmp * (1 << flash_read_uchar (info, FLASH_OFFSET_WMAX_TOUT))) / 1000;
  978. info->flash_id = FLASH_MAN_CFI;
  979. if ((info->interface == FLASH_CFI_X8X16) && (info->chipwidth == FLASH_CFI_BY8)) {
  980. info->portwidth >>= 1; /* XXX - Need to test on x8/x16 in parallel. */
  981. }
  982. }
  983. flash_write_cmd (info, 0, 0, FLASH_CMD_RESET);
  984. return (info->size);
  985. }
  986. /*-----------------------------------------------------------------------
  987. */
  988. static int flash_write_cfiword (flash_info_t * info, ulong dest,
  989. cfiword_t cword)
  990. {
  991. cfiptr_t ctladdr;
  992. cfiptr_t cptr;
  993. int flag;
  994. ctladdr.cp = flash_make_addr (info, 0, 0);
  995. cptr.cp = (uchar *) dest;
  996. /* Check if Flash is (sufficiently) erased */
  997. switch (info->portwidth) {
  998. case FLASH_CFI_8BIT:
  999. flag = ((cptr.cp[0] & cword.c) == cword.c);
  1000. break;
  1001. case FLASH_CFI_16BIT:
  1002. flag = ((cptr.wp[0] & cword.w) == cword.w);
  1003. break;
  1004. case FLASH_CFI_32BIT:
  1005. flag = ((cptr.lp[0] & cword.l) == cword.l);
  1006. break;
  1007. case FLASH_CFI_64BIT:
  1008. flag = ((cptr.llp[0] & cword.ll) == cword.ll);
  1009. break;
  1010. default:
  1011. return 2;
  1012. }
  1013. if (!flag)
  1014. return 2;
  1015. /* Disable interrupts which might cause a timeout here */
  1016. flag = disable_interrupts ();
  1017. switch (info->vendor) {
  1018. case CFI_CMDSET_INTEL_EXTENDED:
  1019. case CFI_CMDSET_INTEL_STANDARD:
  1020. flash_write_cmd (info, 0, 0, FLASH_CMD_CLEAR_STATUS);
  1021. flash_write_cmd (info, 0, 0, FLASH_CMD_WRITE);
  1022. break;
  1023. case CFI_CMDSET_AMD_EXTENDED:
  1024. case CFI_CMDSET_AMD_STANDARD:
  1025. flash_unlock_seq (info, 0);
  1026. flash_write_cmd (info, 0, AMD_ADDR_START, AMD_CMD_WRITE);
  1027. break;
  1028. }
  1029. switch (info->portwidth) {
  1030. case FLASH_CFI_8BIT:
  1031. cptr.cp[0] = cword.c;
  1032. break;
  1033. case FLASH_CFI_16BIT:
  1034. cptr.wp[0] = cword.w;
  1035. break;
  1036. case FLASH_CFI_32BIT:
  1037. cptr.lp[0] = cword.l;
  1038. break;
  1039. case FLASH_CFI_64BIT:
  1040. cptr.llp[0] = cword.ll;
  1041. break;
  1042. }
  1043. /* re-enable interrupts if necessary */
  1044. if (flag)
  1045. enable_interrupts ();
  1046. return flash_full_status_check (info, 0, info->write_tout, "write");
  1047. }
  1048. #ifdef CFG_FLASH_USE_BUFFER_WRITE
  1049. /* loop through the sectors from the highest address
  1050. * when the passed address is greater or equal to the sector address
  1051. * we have a match
  1052. */
  1053. static flash_sect_t find_sector (flash_info_t * info, ulong addr)
  1054. {
  1055. flash_sect_t sector;
  1056. for (sector = info->sector_count - 1; sector >= 0; sector--) {
  1057. if (addr >= info->start[sector])
  1058. break;
  1059. }
  1060. return sector;
  1061. }
  1062. static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp,
  1063. int len)
  1064. {
  1065. flash_sect_t sector;
  1066. int cnt;
  1067. int retcode;
  1068. volatile cfiptr_t src;
  1069. volatile cfiptr_t dst;
  1070. /* buffered writes in the AMD chip set is not supported yet */
  1071. if((info->vendor == CFI_CMDSET_AMD_STANDARD) ||
  1072. (info->vendor == CFI_CMDSET_AMD_EXTENDED))
  1073. return ERR_INVAL;
  1074. src.cp = cp;
  1075. dst.cp = (uchar *) dest;
  1076. sector = find_sector (info, dest);
  1077. flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
  1078. flash_write_cmd (info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER);
  1079. if ((retcode =
  1080. flash_status_check (info, sector, info->buffer_write_tout,
  1081. "write to buffer")) == ERR_OK) {
  1082. /* reduce the number of loops by the width of the port */
  1083. switch (info->portwidth) {
  1084. case FLASH_CFI_8BIT:
  1085. cnt = len;
  1086. break;
  1087. case FLASH_CFI_16BIT:
  1088. cnt = len >> 1;
  1089. break;
  1090. case FLASH_CFI_32BIT:
  1091. cnt = len >> 2;
  1092. break;
  1093. case FLASH_CFI_64BIT:
  1094. cnt = len >> 3;
  1095. break;
  1096. default:
  1097. return ERR_INVAL;
  1098. break;
  1099. }
  1100. flash_write_cmd (info, sector, 0, (uchar) cnt - 1);
  1101. while (cnt-- > 0) {
  1102. switch (info->portwidth) {
  1103. case FLASH_CFI_8BIT:
  1104. *dst.cp++ = *src.cp++;
  1105. break;
  1106. case FLASH_CFI_16BIT:
  1107. *dst.wp++ = *src.wp++;
  1108. break;
  1109. case FLASH_CFI_32BIT:
  1110. *dst.lp++ = *src.lp++;
  1111. break;
  1112. case FLASH_CFI_64BIT:
  1113. *dst.llp++ = *src.llp++;
  1114. break;
  1115. default:
  1116. return ERR_INVAL;
  1117. break;
  1118. }
  1119. }
  1120. flash_write_cmd (info, sector, 0,
  1121. FLASH_CMD_WRITE_BUFFER_CONFIRM);
  1122. retcode =
  1123. flash_full_status_check (info, sector,
  1124. info->buffer_write_tout,
  1125. "buffer write");
  1126. }
  1127. flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
  1128. return retcode;
  1129. }
  1130. #endif /* CFG_FLASH_USE_BUFFER_WRITE */
  1131. #endif /* CFG_FLASH_CFI */