rk_spi.c 9.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382
  1. /*
  2. * spi driver for rockchip
  3. *
  4. * (C) Copyright 2015 Google, Inc
  5. *
  6. * (C) Copyright 2008-2013 Rockchip Electronics
  7. * Peter, Software Engineering, <superpeter.cai@gmail.com>.
  8. *
  9. * SPDX-License-Identifier: GPL-2.0+
  10. */
  11. #include <common.h>
  12. #include <clk.h>
  13. #include <dm.h>
  14. #include <errno.h>
  15. #include <spi.h>
  16. #include <asm/errno.h>
  17. #include <asm/io.h>
  18. #include <asm/arch/clock.h>
  19. #include <asm/arch/periph.h>
  20. #include <dm/pinctrl.h>
  21. #include "rk_spi.h"
  22. DECLARE_GLOBAL_DATA_PTR;
  23. /* Change to 1 to output registers at the start of each transaction */
  24. #define DEBUG_RK_SPI 0
  25. struct rockchip_spi_platdata {
  26. s32 frequency; /* Default clock frequency, -1 for none */
  27. fdt_addr_t base;
  28. uint deactivate_delay_us; /* Delay to wait after deactivate */
  29. uint activate_delay_us; /* Delay to wait after activate */
  30. };
  31. struct rockchip_spi_priv {
  32. struct rockchip_spi *regs;
  33. struct udevice *clk;
  34. int clk_id;
  35. unsigned int max_freq;
  36. unsigned int mode;
  37. ulong last_transaction_us; /* Time of last transaction end */
  38. u8 bits_per_word; /* max 16 bits per word */
  39. u8 n_bytes;
  40. unsigned int speed_hz;
  41. unsigned int last_speed_hz;
  42. unsigned int tmode;
  43. uint input_rate;
  44. };
  45. #define SPI_FIFO_DEPTH 32
  46. static void rkspi_dump_regs(struct rockchip_spi *regs)
  47. {
  48. debug("ctrl0: \t\t0x%08x\n", readl(&regs->ctrlr0));
  49. debug("ctrl1: \t\t0x%08x\n", readl(&regs->ctrlr1));
  50. debug("ssienr: \t\t0x%08x\n", readl(&regs->enr));
  51. debug("ser: \t\t0x%08x\n", readl(&regs->ser));
  52. debug("baudr: \t\t0x%08x\n", readl(&regs->baudr));
  53. debug("txftlr: \t\t0x%08x\n", readl(&regs->txftlr));
  54. debug("rxftlr: \t\t0x%08x\n", readl(&regs->rxftlr));
  55. debug("txflr: \t\t0x%08x\n", readl(&regs->txflr));
  56. debug("rxflr: \t\t0x%08x\n", readl(&regs->rxflr));
  57. debug("sr: \t\t0x%08x\n", readl(&regs->sr));
  58. debug("imr: \t\t0x%08x\n", readl(&regs->imr));
  59. debug("isr: \t\t0x%08x\n", readl(&regs->isr));
  60. debug("dmacr: \t\t0x%08x\n", readl(&regs->dmacr));
  61. debug("dmatdlr: \t0x%08x\n", readl(&regs->dmatdlr));
  62. debug("dmardlr: \t0x%08x\n", readl(&regs->dmardlr));
  63. }
  64. static void rkspi_enable_chip(struct rockchip_spi *regs, bool enable)
  65. {
  66. writel(enable ? 1 : 0, &regs->enr);
  67. }
  68. static void rkspi_set_clk(struct rockchip_spi_priv *priv, uint speed)
  69. {
  70. uint clk_div;
  71. clk_div = clk_get_divisor(priv->input_rate, speed);
  72. debug("spi speed %u, div %u\n", speed, clk_div);
  73. writel(clk_div, &priv->regs->baudr);
  74. priv->last_speed_hz = speed;
  75. }
  76. static int rkspi_wait_till_not_busy(struct rockchip_spi *regs)
  77. {
  78. unsigned long start;
  79. start = get_timer(0);
  80. while (readl(&regs->sr) & SR_BUSY) {
  81. if (get_timer(start) > ROCKCHIP_SPI_TIMEOUT_MS) {
  82. debug("RK SPI: Status keeps busy for 1000us after a read/write!\n");
  83. return -ETIMEDOUT;
  84. }
  85. }
  86. return 0;
  87. }
  88. static void spi_cs_activate(struct udevice *dev, uint cs)
  89. {
  90. struct udevice *bus = dev->parent;
  91. struct rockchip_spi_platdata *plat = bus->platdata;
  92. struct rockchip_spi_priv *priv = dev_get_priv(bus);
  93. struct rockchip_spi *regs = priv->regs;
  94. debug("activate cs%u\n", cs);
  95. writel(1 << cs, &regs->ser);
  96. if (plat->activate_delay_us)
  97. udelay(plat->activate_delay_us);
  98. }
  99. static void spi_cs_deactivate(struct udevice *dev, uint cs)
  100. {
  101. struct udevice *bus = dev->parent;
  102. struct rockchip_spi_platdata *plat = bus->platdata;
  103. struct rockchip_spi_priv *priv = dev_get_priv(bus);
  104. struct rockchip_spi *regs = priv->regs;
  105. debug("deactivate cs%u\n", cs);
  106. writel(0, &regs->ser);
  107. /* Remember time of this transaction so we can honour the bus delay */
  108. if (plat->deactivate_delay_us)
  109. priv->last_transaction_us = timer_get_us();
  110. }
  111. static int rockchip_spi_ofdata_to_platdata(struct udevice *bus)
  112. {
  113. struct rockchip_spi_platdata *plat = bus->platdata;
  114. struct rockchip_spi_priv *priv = dev_get_priv(bus);
  115. const void *blob = gd->fdt_blob;
  116. int node = bus->of_offset;
  117. int ret;
  118. plat->base = dev_get_addr(bus);
  119. ret = clk_get_by_index(bus, 0, &priv->clk);
  120. if (ret < 0) {
  121. debug("%s: Could not get clock for %s: %d\n", __func__,
  122. bus->name, ret);
  123. return ret;
  124. }
  125. priv->clk_id = ret;
  126. plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
  127. 50000000);
  128. plat->deactivate_delay_us = fdtdec_get_int(blob, node,
  129. "spi-deactivate-delay", 0);
  130. plat->activate_delay_us = fdtdec_get_int(blob, node,
  131. "spi-activate-delay", 0);
  132. debug("%s: base=%x, max-frequency=%d, deactivate_delay=%d\n",
  133. __func__, (uint)plat->base, plat->frequency,
  134. plat->deactivate_delay_us);
  135. return 0;
  136. }
  137. static int rockchip_spi_probe(struct udevice *bus)
  138. {
  139. struct rockchip_spi_platdata *plat = dev_get_platdata(bus);
  140. struct rockchip_spi_priv *priv = dev_get_priv(bus);
  141. int ret;
  142. debug("%s: probe\n", __func__);
  143. priv->regs = (struct rockchip_spi *)plat->base;
  144. priv->last_transaction_us = timer_get_us();
  145. priv->max_freq = plat->frequency;
  146. /*
  147. * Use 99 MHz as our clock since it divides nicely into 594 MHz which
  148. * is the assumed speed for CLK_GENERAL.
  149. */
  150. ret = clk_set_periph_rate(priv->clk, priv->clk_id, 99000000);
  151. if (ret < 0) {
  152. debug("%s: Failed to set clock: %d\n", __func__, ret);
  153. return ret;
  154. }
  155. priv->input_rate = ret;
  156. debug("%s: rate = %u\n", __func__, priv->input_rate);
  157. priv->bits_per_word = 8;
  158. priv->tmode = TMOD_TR; /* Tx & Rx */
  159. return 0;
  160. }
  161. static int rockchip_spi_claim_bus(struct udevice *dev)
  162. {
  163. struct udevice *bus = dev->parent;
  164. struct rockchip_spi_priv *priv = dev_get_priv(bus);
  165. struct rockchip_spi *regs = priv->regs;
  166. u8 spi_dfs, spi_tf;
  167. uint ctrlr0;
  168. /* Disable the SPI hardware */
  169. rkspi_enable_chip(regs, 0);
  170. switch (priv->bits_per_word) {
  171. case 8:
  172. priv->n_bytes = 1;
  173. spi_dfs = DFS_8BIT;
  174. spi_tf = HALF_WORD_OFF;
  175. break;
  176. case 16:
  177. priv->n_bytes = 2;
  178. spi_dfs = DFS_16BIT;
  179. spi_tf = HALF_WORD_ON;
  180. break;
  181. default:
  182. debug("%s: unsupported bits: %dbits\n", __func__,
  183. priv->bits_per_word);
  184. return -EPROTONOSUPPORT;
  185. }
  186. if (priv->speed_hz != priv->last_speed_hz)
  187. rkspi_set_clk(priv, priv->speed_hz);
  188. /* Operation Mode */
  189. ctrlr0 = OMOD_MASTER << OMOD_SHIFT;
  190. /* Data Frame Size */
  191. ctrlr0 |= spi_dfs << DFS_SHIFT;
  192. /* set SPI mode 0..3 */
  193. if (priv->mode & SPI_CPOL)
  194. ctrlr0 |= SCOL_HIGH << SCOL_SHIFT;
  195. if (priv->mode & SPI_CPHA)
  196. ctrlr0 |= SCPH_TOGSTA << SCPH_SHIFT;
  197. /* Chip Select Mode */
  198. ctrlr0 |= CSM_KEEP << CSM_SHIFT;
  199. /* SSN to Sclk_out delay */
  200. ctrlr0 |= SSN_DELAY_ONE << SSN_DELAY_SHIFT;
  201. /* Serial Endian Mode */
  202. ctrlr0 |= SEM_LITTLE << SEM_SHIFT;
  203. /* First Bit Mode */
  204. ctrlr0 |= FBM_MSB << FBM_SHIFT;
  205. /* Byte and Halfword Transform */
  206. ctrlr0 |= spi_tf << HALF_WORD_TX_SHIFT;
  207. /* Rxd Sample Delay */
  208. ctrlr0 |= 0 << RXDSD_SHIFT;
  209. /* Frame Format */
  210. ctrlr0 |= FRF_SPI << FRF_SHIFT;
  211. /* Tx and Rx mode */
  212. ctrlr0 |= (priv->tmode & TMOD_MASK) << TMOD_SHIFT;
  213. writel(ctrlr0, &regs->ctrlr0);
  214. return 0;
  215. }
  216. static int rockchip_spi_release_bus(struct udevice *dev)
  217. {
  218. struct udevice *bus = dev->parent;
  219. struct rockchip_spi_priv *priv = dev_get_priv(bus);
  220. rkspi_enable_chip(priv->regs, false);
  221. return 0;
  222. }
  223. static int rockchip_spi_xfer(struct udevice *dev, unsigned int bitlen,
  224. const void *dout, void *din, unsigned long flags)
  225. {
  226. struct udevice *bus = dev->parent;
  227. struct rockchip_spi_priv *priv = dev_get_priv(bus);
  228. struct rockchip_spi *regs = priv->regs;
  229. struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
  230. int len = bitlen >> 3;
  231. const u8 *out = dout;
  232. u8 *in = din;
  233. int toread, towrite;
  234. int ret;
  235. debug("%s: dout=%p, din=%p, len=%x, flags=%lx\n", __func__, dout, din,
  236. len, flags);
  237. if (DEBUG_RK_SPI)
  238. rkspi_dump_regs(regs);
  239. /* Assert CS before transfer */
  240. if (flags & SPI_XFER_BEGIN)
  241. spi_cs_activate(dev, slave_plat->cs);
  242. while (len > 0) {
  243. int todo = min(len, 0xffff);
  244. rkspi_enable_chip(regs, false);
  245. writel(todo - 1, &regs->ctrlr1);
  246. rkspi_enable_chip(regs, true);
  247. toread = todo;
  248. towrite = todo;
  249. while (toread || towrite) {
  250. u32 status = readl(&regs->sr);
  251. if (towrite && !(status & SR_TF_FULL)) {
  252. writel(out ? *out++ : 0, regs->txdr);
  253. towrite--;
  254. }
  255. if (toread && !(status & SR_RF_EMPT)) {
  256. u32 byte = readl(regs->rxdr);
  257. if (in)
  258. *in++ = byte;
  259. toread--;
  260. }
  261. }
  262. ret = rkspi_wait_till_not_busy(regs);
  263. if (ret)
  264. break;
  265. len -= todo;
  266. }
  267. /* Deassert CS after transfer */
  268. if (flags & SPI_XFER_END)
  269. spi_cs_deactivate(dev, slave_plat->cs);
  270. rkspi_enable_chip(regs, false);
  271. return ret;
  272. }
  273. static int rockchip_spi_set_speed(struct udevice *bus, uint speed)
  274. {
  275. struct rockchip_spi_priv *priv = dev_get_priv(bus);
  276. if (speed > ROCKCHIP_SPI_MAX_RATE)
  277. return -EINVAL;
  278. if (speed > priv->max_freq)
  279. speed = priv->max_freq;
  280. priv->speed_hz = speed;
  281. return 0;
  282. }
  283. static int rockchip_spi_set_mode(struct udevice *bus, uint mode)
  284. {
  285. struct rockchip_spi_priv *priv = dev_get_priv(bus);
  286. priv->mode = mode;
  287. return 0;
  288. }
  289. static const struct dm_spi_ops rockchip_spi_ops = {
  290. .claim_bus = rockchip_spi_claim_bus,
  291. .release_bus = rockchip_spi_release_bus,
  292. .xfer = rockchip_spi_xfer,
  293. .set_speed = rockchip_spi_set_speed,
  294. .set_mode = rockchip_spi_set_mode,
  295. /*
  296. * cs_info is not needed, since we require all chip selects to be
  297. * in the device tree explicitly
  298. */
  299. };
  300. static const struct udevice_id rockchip_spi_ids[] = {
  301. { .compatible = "rockchip,rk3288-spi" },
  302. { }
  303. };
  304. U_BOOT_DRIVER(rockchip_spi) = {
  305. .name = "rockchip_spi",
  306. .id = UCLASS_SPI,
  307. .of_match = rockchip_spi_ids,
  308. .ops = &rockchip_spi_ops,
  309. .ofdata_to_platdata = rockchip_spi_ofdata_to_platdata,
  310. .platdata_auto_alloc_size = sizeof(struct rockchip_spi_platdata),
  311. .priv_auto_alloc_size = sizeof(struct rockchip_spi_priv),
  312. .probe = rockchip_spi_probe,
  313. };