fsl_serdes.h 2.2 KB

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  1. /*
  2. * Copyright 2010 Freescale Semiconductor, Inc.
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #ifndef __FSL_SERDES_H
  7. #define __FSL_SERDES_H
  8. #include <config.h>
  9. enum srds_prtcl {
  10. NONE = 0,
  11. PCIE1,
  12. PCIE2,
  13. PCIE3,
  14. PCIE4,
  15. SATA1,
  16. SATA2,
  17. SRIO1,
  18. SRIO2,
  19. SGMII_FM1_DTSEC1,
  20. SGMII_FM1_DTSEC2,
  21. SGMII_FM1_DTSEC3,
  22. SGMII_FM1_DTSEC4,
  23. SGMII_FM1_DTSEC5,
  24. SGMII_FM1_DTSEC6,
  25. SGMII_FM1_DTSEC9,
  26. SGMII_FM1_DTSEC10,
  27. SGMII_FM2_DTSEC1,
  28. SGMII_FM2_DTSEC2,
  29. SGMII_FM2_DTSEC3,
  30. SGMII_FM2_DTSEC4,
  31. SGMII_FM2_DTSEC5,
  32. SGMII_FM2_DTSEC6,
  33. SGMII_FM2_DTSEC9,
  34. SGMII_FM2_DTSEC10,
  35. SGMII_TSEC1,
  36. SGMII_TSEC2,
  37. SGMII_TSEC3,
  38. SGMII_TSEC4,
  39. XAUI_FM1,
  40. XAUI_FM2,
  41. AURORA,
  42. CPRI1,
  43. CPRI2,
  44. CPRI3,
  45. CPRI4,
  46. CPRI5,
  47. CPRI6,
  48. CPRI7,
  49. CPRI8,
  50. XAUI_FM1_MAC9,
  51. XAUI_FM1_MAC10,
  52. XAUI_FM2_MAC9,
  53. XAUI_FM2_MAC10,
  54. HIGIG_FM1_MAC9,
  55. HIGIG_FM1_MAC10,
  56. HIGIG_FM2_MAC9,
  57. HIGIG_FM2_MAC10,
  58. QSGMII_FM1_A, /* A indicates MACs 1-4 */
  59. QSGMII_FM1_B, /* B indicates MACs 5,6,9,10 */
  60. QSGMII_FM2_A,
  61. QSGMII_FM2_B,
  62. XFI_FM1_MAC1,
  63. XFI_FM1_MAC2,
  64. XFI_FM1_MAC9,
  65. XFI_FM1_MAC10,
  66. XFI_FM2_MAC9,
  67. XFI_FM2_MAC10,
  68. INTERLAKEN,
  69. QSGMII_SW1_A, /* Indicates ports on L2 Switch */
  70. QSGMII_SW1_B,
  71. SGMII_2500_FM1_DTSEC1,
  72. SGMII_2500_FM1_DTSEC2,
  73. SGMII_2500_FM1_DTSEC3,
  74. SGMII_2500_FM1_DTSEC4,
  75. SGMII_2500_FM1_DTSEC5,
  76. SGMII_2500_FM1_DTSEC6,
  77. SGMII_2500_FM1_DTSEC9,
  78. SGMII_2500_FM1_DTSEC10,
  79. SGMII_2500_FM2_DTSEC1,
  80. SGMII_2500_FM2_DTSEC2,
  81. SGMII_2500_FM2_DTSEC3,
  82. SGMII_2500_FM2_DTSEC4,
  83. SGMII_2500_FM2_DTSEC5,
  84. SGMII_2500_FM2_DTSEC6,
  85. SGMII_2500_FM2_DTSEC9,
  86. SGMII_2500_FM2_DTSEC10,
  87. SGMII_SW1_MAC1,
  88. SGMII_SW1_MAC2,
  89. SGMII_SW1_MAC3,
  90. SGMII_SW1_MAC4,
  91. SGMII_SW1_MAC5,
  92. SGMII_SW1_MAC6,
  93. SERDES_PRCTL_COUNT /* Keep this item the last one */
  94. };
  95. enum srds {
  96. FSL_SRDS_1 = 0,
  97. FSL_SRDS_2 = 1,
  98. FSL_SRDS_3 = 2,
  99. FSL_SRDS_4 = 3,
  100. };
  101. int is_serdes_configured(enum srds_prtcl device);
  102. void fsl_serdes_init(void);
  103. const char *serdes_clock_to_string(u32 clock);
  104. #ifdef CONFIG_FSL_CORENET
  105. #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
  106. int serdes_get_first_lane(u32 sd, enum srds_prtcl device);
  107. enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
  108. #else
  109. int serdes_get_first_lane(enum srds_prtcl device);
  110. #endif
  111. #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
  112. void serdes_reset_rx(enum srds_prtcl device);
  113. #endif
  114. #endif
  115. #endif /* __FSL_SERDES_H */