xilinx.c 6.6 KB

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  1. /*
  2. * (C) Copyright 2012-2013, Xilinx, Michal Simek
  3. *
  4. * (C) Copyright 2002
  5. * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
  6. * Keith Outwater, keith_outwater@mvis.com
  7. *
  8. * SPDX-License-Identifier: GPL-2.0+
  9. */
  10. /*
  11. * Xilinx FPGA support
  12. */
  13. #include <common.h>
  14. #include <fpga.h>
  15. #include <virtex2.h>
  16. #include <spartan2.h>
  17. #include <spartan3.h>
  18. #include <zynqpl.h>
  19. /* Local Static Functions */
  20. static int xilinx_validate(xilinx_desc *desc, char *fn);
  21. /* ------------------------------------------------------------------------- */
  22. int fpga_loadbitstream(int devnum, char *fpgadata, size_t size,
  23. bitstream_type bstype)
  24. {
  25. unsigned int length;
  26. unsigned int swapsize;
  27. char buffer[80];
  28. unsigned char *dataptr;
  29. unsigned int i;
  30. const fpga_desc *desc;
  31. xilinx_desc *xdesc;
  32. dataptr = (unsigned char *)fpgadata;
  33. /* Find out fpga_description */
  34. desc = fpga_validate(devnum, dataptr, 0, (char *)__func__);
  35. /* Assign xilinx device description */
  36. xdesc = desc->devdesc;
  37. /* skip the first bytes of the bitsteam, their meaning is unknown */
  38. length = (*dataptr << 8) + *(dataptr + 1);
  39. dataptr += 2;
  40. dataptr += length;
  41. /* get design name (identifier, length, string) */
  42. length = (*dataptr << 8) + *(dataptr + 1);
  43. dataptr += 2;
  44. if (*dataptr++ != 0x61) {
  45. debug("%s: Design name id not recognized in bitstream\n",
  46. __func__);
  47. return FPGA_FAIL;
  48. }
  49. length = (*dataptr << 8) + *(dataptr + 1);
  50. dataptr += 2;
  51. for (i = 0; i < length; i++)
  52. buffer[i] = *dataptr++;
  53. printf(" design filename = \"%s\"\n", buffer);
  54. /* get part number (identifier, length, string) */
  55. if (*dataptr++ != 0x62) {
  56. printf("%s: Part number id not recognized in bitstream\n",
  57. __func__);
  58. return FPGA_FAIL;
  59. }
  60. length = (*dataptr << 8) + *(dataptr + 1);
  61. dataptr += 2;
  62. for (i = 0; i < length; i++)
  63. buffer[i] = *dataptr++;
  64. if (xdesc->name) {
  65. i = strncmp(buffer, xdesc->name, strlen(xdesc->name));
  66. if (i) {
  67. printf("%s: Wrong bitstream ID for this device\n",
  68. __func__);
  69. printf("%s: Bitstream ID %s, current device ID %d/%s\n",
  70. __func__, buffer, devnum, xdesc->name);
  71. return FPGA_FAIL;
  72. }
  73. } else {
  74. printf("%s: Please fill correct device ID to xilinx_desc\n",
  75. __func__);
  76. }
  77. printf(" part number = \"%s\"\n", buffer);
  78. /* get date (identifier, length, string) */
  79. if (*dataptr++ != 0x63) {
  80. printf("%s: Date identifier not recognized in bitstream\n",
  81. __func__);
  82. return FPGA_FAIL;
  83. }
  84. length = (*dataptr << 8) + *(dataptr+1);
  85. dataptr += 2;
  86. for (i = 0; i < length; i++)
  87. buffer[i] = *dataptr++;
  88. printf(" date = \"%s\"\n", buffer);
  89. /* get time (identifier, length, string) */
  90. if (*dataptr++ != 0x64) {
  91. printf("%s: Time identifier not recognized in bitstream\n",
  92. __func__);
  93. return FPGA_FAIL;
  94. }
  95. length = (*dataptr << 8) + *(dataptr+1);
  96. dataptr += 2;
  97. for (i = 0; i < length; i++)
  98. buffer[i] = *dataptr++;
  99. printf(" time = \"%s\"\n", buffer);
  100. /* get fpga data length (identifier, length) */
  101. if (*dataptr++ != 0x65) {
  102. printf("%s: Data length id not recognized in bitstream\n",
  103. __func__);
  104. return FPGA_FAIL;
  105. }
  106. swapsize = ((unsigned int) *dataptr << 24) +
  107. ((unsigned int) *(dataptr + 1) << 16) +
  108. ((unsigned int) *(dataptr + 2) << 8) +
  109. ((unsigned int) *(dataptr + 3));
  110. dataptr += 4;
  111. printf(" bytes in bitstream = %d\n", swapsize);
  112. return fpga_load(devnum, dataptr, swapsize, bstype);
  113. }
  114. int xilinx_load(xilinx_desc *desc, const void *buf, size_t bsize,
  115. bitstream_type bstype)
  116. {
  117. if (!xilinx_validate (desc, (char *)__FUNCTION__)) {
  118. printf ("%s: Invalid device descriptor\n", __FUNCTION__);
  119. return FPGA_FAIL;
  120. }
  121. return desc->operations->load(desc, buf, bsize, bstype);
  122. }
  123. #if defined(CONFIG_CMD_FPGA_LOADFS)
  124. int xilinx_loadfs(xilinx_desc *desc, const void *buf, size_t bsize,
  125. fpga_fs_info *fpga_fsinfo)
  126. {
  127. if (!xilinx_validate(desc, (char *)__func__)) {
  128. printf("%s: Invalid device descriptor\n", __func__);
  129. return FPGA_FAIL;
  130. }
  131. if (!desc->operations->loadfs)
  132. return FPGA_FAIL;
  133. return desc->operations->loadfs(desc, buf, bsize, fpga_fsinfo);
  134. }
  135. #endif
  136. int xilinx_dump(xilinx_desc *desc, const void *buf, size_t bsize)
  137. {
  138. if (!xilinx_validate (desc, (char *)__FUNCTION__)) {
  139. printf ("%s: Invalid device descriptor\n", __FUNCTION__);
  140. return FPGA_FAIL;
  141. }
  142. return desc->operations->dump(desc, buf, bsize);
  143. }
  144. int xilinx_info(xilinx_desc *desc)
  145. {
  146. int ret_val = FPGA_FAIL;
  147. if (xilinx_validate (desc, (char *)__FUNCTION__)) {
  148. printf ("Family: \t");
  149. switch (desc->family) {
  150. case xilinx_spartan2:
  151. printf ("Spartan-II\n");
  152. break;
  153. case xilinx_spartan3:
  154. printf ("Spartan-III\n");
  155. break;
  156. case xilinx_virtex2:
  157. printf ("Virtex-II\n");
  158. break;
  159. case xilinx_zynq:
  160. printf("Zynq PL\n");
  161. break;
  162. /* Add new family types here */
  163. default:
  164. printf ("Unknown family type, %d\n", desc->family);
  165. }
  166. printf ("Interface type:\t");
  167. switch (desc->iface) {
  168. case slave_serial:
  169. printf ("Slave Serial\n");
  170. break;
  171. case master_serial: /* Not used */
  172. printf ("Master Serial\n");
  173. break;
  174. case slave_parallel:
  175. printf ("Slave Parallel\n");
  176. break;
  177. case jtag_mode: /* Not used */
  178. printf ("JTAG Mode\n");
  179. break;
  180. case slave_selectmap:
  181. printf ("Slave SelectMap Mode\n");
  182. break;
  183. case master_selectmap:
  184. printf ("Master SelectMap Mode\n");
  185. break;
  186. case devcfg:
  187. printf("Device configuration interface (Zynq)\n");
  188. break;
  189. /* Add new interface types here */
  190. default:
  191. printf ("Unsupported interface type, %d\n", desc->iface);
  192. }
  193. printf("Device Size: \t%zd bytes\n"
  194. "Cookie: \t0x%x (%d)\n",
  195. desc->size, desc->cookie, desc->cookie);
  196. if (desc->name)
  197. printf("Device name: \t%s\n", desc->name);
  198. if (desc->iface_fns) {
  199. printf ("Device Function Table @ 0x%p\n", desc->iface_fns);
  200. desc->operations->info(desc);
  201. } else
  202. printf ("No Device Function Table.\n");
  203. ret_val = FPGA_SUCCESS;
  204. } else {
  205. printf ("%s: Invalid device descriptor\n", __FUNCTION__);
  206. }
  207. return ret_val;
  208. }
  209. /* ------------------------------------------------------------------------- */
  210. static int xilinx_validate(xilinx_desc *desc, char *fn)
  211. {
  212. int ret_val = false;
  213. if (desc) {
  214. if ((desc->family > min_xilinx_type) &&
  215. (desc->family < max_xilinx_type)) {
  216. if ((desc->iface > min_xilinx_iface_type) &&
  217. (desc->iface < max_xilinx_iface_type)) {
  218. if (desc->size) {
  219. ret_val = true;
  220. } else
  221. printf ("%s: NULL part size\n", fn);
  222. } else
  223. printf ("%s: Invalid Interface type, %d\n",
  224. fn, desc->iface);
  225. } else
  226. printf ("%s: Invalid family type, %d\n", fn, desc->family);
  227. } else
  228. printf ("%s: NULL descriptor!\n", fn);
  229. return ret_val;
  230. }