ddr.c 2.1 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2013 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <asm/mmu.h>
  7. #include <asm/immap_85xx.h>
  8. #include <asm/processor.h>
  9. #include <fsl_ddr_sdram.h>
  10. #include <fsl_ddr_dimm_params.h>
  11. #include <asm/io.h>
  12. #include <asm/fsl_law.h>
  13. /* Fixed sdram init -- doesn't use serial presence detect. */
  14. phys_size_t fixed_sdram(void)
  15. {
  16. sys_info_t sysinfo;
  17. char buf[32];
  18. size_t ddr_size;
  19. fsl_ddr_cfg_regs_t ddr_cfg_regs = {
  20. .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
  21. .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
  22. .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
  23. #if CONFIG_CHIP_SELECTS_PER_CTRL > 1
  24. .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
  25. .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
  26. .cs[1].config_2 = CONFIG_SYS_DDR_CS1_CONFIG_2,
  27. #endif
  28. .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3,
  29. .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0,
  30. .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1,
  31. .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2,
  32. .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
  33. .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
  34. .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1,
  35. .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2,
  36. .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
  37. .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL,
  38. .ddr_data_init = CONFIG_SYS_DDR_DATA_INIT,
  39. .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL,
  40. .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
  41. .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
  42. .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
  43. .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
  44. .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
  45. .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
  46. .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
  47. .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
  48. .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
  49. };
  50. get_sys_info(&sysinfo);
  51. printf("Configuring DDR for %s MT/s data rate\n",
  52. strmhz(buf, sysinfo.freq_ddrbus));
  53. ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
  54. fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
  55. if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
  56. ddr_size, LAW_TRGT_IF_DDR_1) < 0) {
  57. printf("ERROR setting Local Access Windows for DDR\n");
  58. return 0;
  59. };
  60. return ddr_size;
  61. }