ddr.c 18 KB

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  1. /*
  2. * Copyright (C) 2014 Gateworks Corporation
  3. * Author: Tim Harvey <tharvey@gateworks.com>
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. #include <common.h>
  8. #include <linux/types.h>
  9. #include <asm/arch/mx6-ddr.h>
  10. #include <asm/arch/sys_proto.h>
  11. #include <asm/io.h>
  12. #include <asm/types.h>
  13. #if defined(CONFIG_MX6SX)
  14. /* Configure MX6SX mmdc iomux */
  15. void mx6sx_dram_iocfg(unsigned width,
  16. const struct mx6sx_iomux_ddr_regs *ddr,
  17. const struct mx6sx_iomux_grp_regs *grp)
  18. {
  19. struct mx6sx_iomux_ddr_regs *mx6_ddr_iomux;
  20. struct mx6sx_iomux_grp_regs *mx6_grp_iomux;
  21. mx6_ddr_iomux = (struct mx6sx_iomux_ddr_regs *)MX6SX_IOM_DDR_BASE;
  22. mx6_grp_iomux = (struct mx6sx_iomux_grp_regs *)MX6SX_IOM_GRP_BASE;
  23. /* DDR IO TYPE */
  24. writel(grp->grp_ddr_type, &mx6_grp_iomux->grp_ddr_type);
  25. writel(grp->grp_ddrpke, &mx6_grp_iomux->grp_ddrpke);
  26. /* CLOCK */
  27. writel(ddr->dram_sdclk_0, &mx6_ddr_iomux->dram_sdclk_0);
  28. /* ADDRESS */
  29. writel(ddr->dram_cas, &mx6_ddr_iomux->dram_cas);
  30. writel(ddr->dram_ras, &mx6_ddr_iomux->dram_ras);
  31. writel(grp->grp_addds, &mx6_grp_iomux->grp_addds);
  32. /* Control */
  33. writel(ddr->dram_reset, &mx6_ddr_iomux->dram_reset);
  34. writel(ddr->dram_sdba2, &mx6_ddr_iomux->dram_sdba2);
  35. writel(ddr->dram_sdcke0, &mx6_ddr_iomux->dram_sdcke0);
  36. writel(ddr->dram_sdcke1, &mx6_ddr_iomux->dram_sdcke1);
  37. writel(ddr->dram_odt0, &mx6_ddr_iomux->dram_odt0);
  38. writel(ddr->dram_odt1, &mx6_ddr_iomux->dram_odt1);
  39. writel(grp->grp_ctlds, &mx6_grp_iomux->grp_ctlds);
  40. /* Data Strobes */
  41. writel(grp->grp_ddrmode_ctl, &mx6_grp_iomux->grp_ddrmode_ctl);
  42. writel(ddr->dram_sdqs0, &mx6_ddr_iomux->dram_sdqs0);
  43. writel(ddr->dram_sdqs1, &mx6_ddr_iomux->dram_sdqs1);
  44. if (width >= 32) {
  45. writel(ddr->dram_sdqs2, &mx6_ddr_iomux->dram_sdqs2);
  46. writel(ddr->dram_sdqs3, &mx6_ddr_iomux->dram_sdqs3);
  47. }
  48. /* Data */
  49. writel(grp->grp_ddrmode, &mx6_grp_iomux->grp_ddrmode);
  50. writel(grp->grp_b0ds, &mx6_grp_iomux->grp_b0ds);
  51. writel(grp->grp_b1ds, &mx6_grp_iomux->grp_b1ds);
  52. if (width >= 32) {
  53. writel(grp->grp_b2ds, &mx6_grp_iomux->grp_b2ds);
  54. writel(grp->grp_b3ds, &mx6_grp_iomux->grp_b3ds);
  55. }
  56. writel(ddr->dram_dqm0, &mx6_ddr_iomux->dram_dqm0);
  57. writel(ddr->dram_dqm1, &mx6_ddr_iomux->dram_dqm1);
  58. if (width >= 32) {
  59. writel(ddr->dram_dqm2, &mx6_ddr_iomux->dram_dqm2);
  60. writel(ddr->dram_dqm3, &mx6_ddr_iomux->dram_dqm3);
  61. }
  62. }
  63. #endif
  64. #if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
  65. /* Configure MX6DQ mmdc iomux */
  66. void mx6dq_dram_iocfg(unsigned width,
  67. const struct mx6dq_iomux_ddr_regs *ddr,
  68. const struct mx6dq_iomux_grp_regs *grp)
  69. {
  70. volatile struct mx6dq_iomux_ddr_regs *mx6_ddr_iomux;
  71. volatile struct mx6dq_iomux_grp_regs *mx6_grp_iomux;
  72. mx6_ddr_iomux = (struct mx6dq_iomux_ddr_regs *)MX6DQ_IOM_DDR_BASE;
  73. mx6_grp_iomux = (struct mx6dq_iomux_grp_regs *)MX6DQ_IOM_GRP_BASE;
  74. /* DDR IO Type */
  75. mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type;
  76. mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke;
  77. /* Clock */
  78. mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0;
  79. mx6_ddr_iomux->dram_sdclk_1 = ddr->dram_sdclk_1;
  80. /* Address */
  81. mx6_ddr_iomux->dram_cas = ddr->dram_cas;
  82. mx6_ddr_iomux->dram_ras = ddr->dram_ras;
  83. mx6_grp_iomux->grp_addds = grp->grp_addds;
  84. /* Control */
  85. mx6_ddr_iomux->dram_reset = ddr->dram_reset;
  86. mx6_ddr_iomux->dram_sdcke0 = ddr->dram_sdcke0;
  87. mx6_ddr_iomux->dram_sdcke1 = ddr->dram_sdcke1;
  88. mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2;
  89. mx6_ddr_iomux->dram_sdodt0 = ddr->dram_sdodt0;
  90. mx6_ddr_iomux->dram_sdodt1 = ddr->dram_sdodt1;
  91. mx6_grp_iomux->grp_ctlds = grp->grp_ctlds;
  92. /* Data Strobes */
  93. mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl;
  94. mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0;
  95. mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1;
  96. if (width >= 32) {
  97. mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2;
  98. mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3;
  99. }
  100. if (width >= 64) {
  101. mx6_ddr_iomux->dram_sdqs4 = ddr->dram_sdqs4;
  102. mx6_ddr_iomux->dram_sdqs5 = ddr->dram_sdqs5;
  103. mx6_ddr_iomux->dram_sdqs6 = ddr->dram_sdqs6;
  104. mx6_ddr_iomux->dram_sdqs7 = ddr->dram_sdqs7;
  105. }
  106. /* Data */
  107. mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode;
  108. mx6_grp_iomux->grp_b0ds = grp->grp_b0ds;
  109. mx6_grp_iomux->grp_b1ds = grp->grp_b1ds;
  110. if (width >= 32) {
  111. mx6_grp_iomux->grp_b2ds = grp->grp_b2ds;
  112. mx6_grp_iomux->grp_b3ds = grp->grp_b3ds;
  113. }
  114. if (width >= 64) {
  115. mx6_grp_iomux->grp_b4ds = grp->grp_b4ds;
  116. mx6_grp_iomux->grp_b5ds = grp->grp_b5ds;
  117. mx6_grp_iomux->grp_b6ds = grp->grp_b6ds;
  118. mx6_grp_iomux->grp_b7ds = grp->grp_b7ds;
  119. }
  120. mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0;
  121. mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1;
  122. if (width >= 32) {
  123. mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2;
  124. mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3;
  125. }
  126. if (width >= 64) {
  127. mx6_ddr_iomux->dram_dqm4 = ddr->dram_dqm4;
  128. mx6_ddr_iomux->dram_dqm5 = ddr->dram_dqm5;
  129. mx6_ddr_iomux->dram_dqm6 = ddr->dram_dqm6;
  130. mx6_ddr_iomux->dram_dqm7 = ddr->dram_dqm7;
  131. }
  132. }
  133. #endif
  134. #if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
  135. /* Configure MX6SDL mmdc iomux */
  136. void mx6sdl_dram_iocfg(unsigned width,
  137. const struct mx6sdl_iomux_ddr_regs *ddr,
  138. const struct mx6sdl_iomux_grp_regs *grp)
  139. {
  140. volatile struct mx6sdl_iomux_ddr_regs *mx6_ddr_iomux;
  141. volatile struct mx6sdl_iomux_grp_regs *mx6_grp_iomux;
  142. mx6_ddr_iomux = (struct mx6sdl_iomux_ddr_regs *)MX6SDL_IOM_DDR_BASE;
  143. mx6_grp_iomux = (struct mx6sdl_iomux_grp_regs *)MX6SDL_IOM_GRP_BASE;
  144. /* DDR IO Type */
  145. mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type;
  146. mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke;
  147. /* Clock */
  148. mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0;
  149. mx6_ddr_iomux->dram_sdclk_1 = ddr->dram_sdclk_1;
  150. /* Address */
  151. mx6_ddr_iomux->dram_cas = ddr->dram_cas;
  152. mx6_ddr_iomux->dram_ras = ddr->dram_ras;
  153. mx6_grp_iomux->grp_addds = grp->grp_addds;
  154. /* Control */
  155. mx6_ddr_iomux->dram_reset = ddr->dram_reset;
  156. mx6_ddr_iomux->dram_sdcke0 = ddr->dram_sdcke0;
  157. mx6_ddr_iomux->dram_sdcke1 = ddr->dram_sdcke1;
  158. mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2;
  159. mx6_ddr_iomux->dram_sdodt0 = ddr->dram_sdodt0;
  160. mx6_ddr_iomux->dram_sdodt1 = ddr->dram_sdodt1;
  161. mx6_grp_iomux->grp_ctlds = grp->grp_ctlds;
  162. /* Data Strobes */
  163. mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl;
  164. mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0;
  165. mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1;
  166. if (width >= 32) {
  167. mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2;
  168. mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3;
  169. }
  170. if (width >= 64) {
  171. mx6_ddr_iomux->dram_sdqs4 = ddr->dram_sdqs4;
  172. mx6_ddr_iomux->dram_sdqs5 = ddr->dram_sdqs5;
  173. mx6_ddr_iomux->dram_sdqs6 = ddr->dram_sdqs6;
  174. mx6_ddr_iomux->dram_sdqs7 = ddr->dram_sdqs7;
  175. }
  176. /* Data */
  177. mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode;
  178. mx6_grp_iomux->grp_b0ds = grp->grp_b0ds;
  179. mx6_grp_iomux->grp_b1ds = grp->grp_b1ds;
  180. if (width >= 32) {
  181. mx6_grp_iomux->grp_b2ds = grp->grp_b2ds;
  182. mx6_grp_iomux->grp_b3ds = grp->grp_b3ds;
  183. }
  184. if (width >= 64) {
  185. mx6_grp_iomux->grp_b4ds = grp->grp_b4ds;
  186. mx6_grp_iomux->grp_b5ds = grp->grp_b5ds;
  187. mx6_grp_iomux->grp_b6ds = grp->grp_b6ds;
  188. mx6_grp_iomux->grp_b7ds = grp->grp_b7ds;
  189. }
  190. mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0;
  191. mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1;
  192. if (width >= 32) {
  193. mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2;
  194. mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3;
  195. }
  196. if (width >= 64) {
  197. mx6_ddr_iomux->dram_dqm4 = ddr->dram_dqm4;
  198. mx6_ddr_iomux->dram_dqm5 = ddr->dram_dqm5;
  199. mx6_ddr_iomux->dram_dqm6 = ddr->dram_dqm6;
  200. mx6_ddr_iomux->dram_dqm7 = ddr->dram_dqm7;
  201. }
  202. }
  203. #endif
  204. /*
  205. * Configure mx6 mmdc registers based on:
  206. * - board-specific memory configuration
  207. * - board-specific calibration data
  208. * - ddr3 chip details
  209. *
  210. * The various calculations here are derived from the Freescale
  211. * i.Mx6DQSDL DDR3 Script Aid spreadsheet (DOC-94917) designed to generate MMDC
  212. * configuration registers based on memory system and memory chip parameters.
  213. *
  214. * The defaults here are those which were specified in the spreadsheet.
  215. * For details on each register, refer to the IMX6DQRM and/or IMX6SDLRM
  216. * section titled MMDC initialization
  217. */
  218. #define MR(val, ba, cmd, cs1) \
  219. ((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba)
  220. #ifdef CONFIG_MX6SX
  221. #define MMDC1(entry, value) do {} while (0)
  222. #else
  223. #define MMDC1(entry, value) do { mmdc1->entry = value; } while (0)
  224. #endif
  225. void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
  226. const struct mx6_mmdc_calibration *calib,
  227. const struct mx6_ddr3_cfg *ddr3_cfg)
  228. {
  229. volatile struct mmdc_p_regs *mmdc0;
  230. #ifndef CONFIG_MX6SX
  231. volatile struct mmdc_p_regs *mmdc1;
  232. #endif
  233. u32 val;
  234. u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd;
  235. u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl;
  236. u8 todt_idle_off = 0x4; /* from DDR3 Script Aid spreadsheet */
  237. u16 trcd, trc, tras, twr, tmrd, trtp, trp, twtr, trfc, txs, txpr;
  238. u16 cs0_end;
  239. u16 tdllk = 0x1ff; /* DLL locking time: 512 cycles (JEDEC DDR3) */
  240. u8 coladdr;
  241. int clkper; /* clock period in picoseconds */
  242. int clock; /* clock freq in mHz */
  243. int cs;
  244. mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
  245. #ifndef CONFIG_MX6SX
  246. mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
  247. #endif
  248. /* MX6D/MX6Q: 1066 MHz memory clock, clkper = 1.894ns = 1894ps */
  249. if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) {
  250. clock = 528;
  251. tcwl = 4;
  252. }
  253. /* MX6S/MX6DL: 800 MHz memory clock, clkper = 2.5ns = 2500ps */
  254. else {
  255. clock = 400;
  256. tcwl = 3;
  257. }
  258. clkper = (1000 * 1000) / clock; /* pico seconds */
  259. todtlon = tcwl;
  260. taxpd = tcwl;
  261. tanpd = tcwl;
  262. switch (ddr3_cfg->density) {
  263. case 1: /* 1Gb per chip */
  264. trfc = DIV_ROUND_UP(110000, clkper) - 1;
  265. txs = DIV_ROUND_UP(120000, clkper) - 1;
  266. break;
  267. case 2: /* 2Gb per chip */
  268. trfc = DIV_ROUND_UP(160000, clkper) - 1;
  269. txs = DIV_ROUND_UP(170000, clkper) - 1;
  270. break;
  271. case 4: /* 4Gb per chip */
  272. trfc = DIV_ROUND_UP(260000, clkper) - 1;
  273. txs = DIV_ROUND_UP(270000, clkper) - 1;
  274. break;
  275. case 8: /* 8Gb per chip */
  276. trfc = DIV_ROUND_UP(350000, clkper) - 1;
  277. txs = DIV_ROUND_UP(360000, clkper) - 1;
  278. break;
  279. default:
  280. /* invalid density */
  281. puts("invalid chip density\n");
  282. hang();
  283. break;
  284. }
  285. txpr = txs;
  286. switch (ddr3_cfg->mem_speed) {
  287. case 800:
  288. txp = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1;
  289. tcke = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1;
  290. if (ddr3_cfg->pagesz == 1) {
  291. tfaw = DIV_ROUND_UP(40000, clkper) - 1;
  292. trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1;
  293. } else {
  294. tfaw = DIV_ROUND_UP(50000, clkper) - 1;
  295. trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1;
  296. }
  297. break;
  298. case 1066:
  299. txp = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1;
  300. tcke = DIV_ROUND_UP(max(3 * clkper, 5625), clkper) - 1;
  301. if (ddr3_cfg->pagesz == 1) {
  302. tfaw = DIV_ROUND_UP(37500, clkper) - 1;
  303. trrd = DIV_ROUND_UP(max(4 * clkper, 7500), clkper) - 1;
  304. } else {
  305. tfaw = DIV_ROUND_UP(50000, clkper) - 1;
  306. trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1;
  307. }
  308. break;
  309. case 1333:
  310. txp = DIV_ROUND_UP(max(3 * clkper, 6000), clkper) - 1;
  311. tcke = DIV_ROUND_UP(max(3 * clkper, 5625), clkper) - 1;
  312. if (ddr3_cfg->pagesz == 1) {
  313. tfaw = DIV_ROUND_UP(30000, clkper) - 1;
  314. trrd = DIV_ROUND_UP(max(4 * clkper, 6000), clkper) - 1;
  315. } else {
  316. tfaw = DIV_ROUND_UP(45000, clkper) - 1;
  317. trrd = DIV_ROUND_UP(max(4 * clkper, 7500), clkper) - 1;
  318. }
  319. break;
  320. case 1600:
  321. txp = DIV_ROUND_UP(max(3 * clkper, 6000), clkper) - 1;
  322. tcke = DIV_ROUND_UP(max(3 * clkper, 5000), clkper) - 1;
  323. if (ddr3_cfg->pagesz == 1) {
  324. tfaw = DIV_ROUND_UP(30000, clkper) - 1;
  325. trrd = DIV_ROUND_UP(max(4 * clkper, 6000), clkper) - 1;
  326. } else {
  327. tfaw = DIV_ROUND_UP(40000, clkper) - 1;
  328. trrd = DIV_ROUND_UP(max(4 * clkper, 7500), clkper) - 1;
  329. }
  330. break;
  331. default:
  332. puts("invalid memory speed\n");
  333. hang();
  334. break;
  335. }
  336. txpdll = DIV_ROUND_UP(max(10 * clkper, 24000), clkper) - 1;
  337. tcksre = DIV_ROUND_UP(max(5 * clkper, 10000), clkper);
  338. taonpd = DIV_ROUND_UP(2000, clkper) - 1;
  339. tcksrx = tcksre;
  340. taofpd = taonpd;
  341. twr = DIV_ROUND_UP(15000, clkper) - 1;
  342. tmrd = DIV_ROUND_UP(max(12 * clkper, 15000), clkper) - 1;
  343. trc = DIV_ROUND_UP(ddr3_cfg->trcmin, clkper / 10) - 1;
  344. tras = DIV_ROUND_UP(ddr3_cfg->trasmin, clkper / 10) - 1;
  345. tcl = DIV_ROUND_UP(ddr3_cfg->trcd, clkper / 10) - 3;
  346. trp = DIV_ROUND_UP(ddr3_cfg->trcd, clkper / 10) - 1;
  347. twtr = ROUND(max(4 * clkper, 7500) / clkper, 1) - 1;
  348. trcd = trp;
  349. trtp = twtr;
  350. cs0_end = 4 * sysinfo->cs_density - 1;
  351. debug("density:%d Gb (%d Gb per chip)\n",
  352. sysinfo->cs_density, ddr3_cfg->density);
  353. debug("clock: %dMHz (%d ps)\n", clock, clkper);
  354. debug("memspd:%d\n", ddr3_cfg->mem_speed);
  355. debug("tcke=%d\n", tcke);
  356. debug("tcksrx=%d\n", tcksrx);
  357. debug("tcksre=%d\n", tcksre);
  358. debug("taofpd=%d\n", taofpd);
  359. debug("taonpd=%d\n", taonpd);
  360. debug("todtlon=%d\n", todtlon);
  361. debug("tanpd=%d\n", tanpd);
  362. debug("taxpd=%d\n", taxpd);
  363. debug("trfc=%d\n", trfc);
  364. debug("txs=%d\n", txs);
  365. debug("txp=%d\n", txp);
  366. debug("txpdll=%d\n", txpdll);
  367. debug("tfaw=%d\n", tfaw);
  368. debug("tcl=%d\n", tcl);
  369. debug("trcd=%d\n", trcd);
  370. debug("trp=%d\n", trp);
  371. debug("trc=%d\n", trc);
  372. debug("tras=%d\n", tras);
  373. debug("twr=%d\n", twr);
  374. debug("tmrd=%d\n", tmrd);
  375. debug("tcwl=%d\n", tcwl);
  376. debug("tdllk=%d\n", tdllk);
  377. debug("trtp=%d\n", trtp);
  378. debug("twtr=%d\n", twtr);
  379. debug("trrd=%d\n", trrd);
  380. debug("txpr=%d\n", txpr);
  381. debug("cs0_end=%d\n", cs0_end);
  382. debug("ncs=%d\n", sysinfo->ncs);
  383. debug("Rtt_wr=%d\n", sysinfo->rtt_wr);
  384. debug("Rtt_nom=%d\n", sysinfo->rtt_nom);
  385. debug("SRT=%d\n", ddr3_cfg->SRT);
  386. debug("tcl=%d\n", tcl);
  387. debug("twr=%d\n", twr);
  388. /*
  389. * board-specific configuration:
  390. * These values are determined empirically and vary per board layout
  391. * see:
  392. * appnote, ddr3 spreadsheet
  393. */
  394. mmdc0->mpwldectrl0 = calib->p0_mpwldectrl0;
  395. mmdc0->mpwldectrl1 = calib->p0_mpwldectrl1;
  396. mmdc0->mpdgctrl0 = calib->p0_mpdgctrl0;
  397. mmdc0->mpdgctrl1 = calib->p0_mpdgctrl1;
  398. mmdc0->mprddlctl = calib->p0_mprddlctl;
  399. mmdc0->mpwrdlctl = calib->p0_mpwrdlctl;
  400. if (sysinfo->dsize > 1) {
  401. MMDC1(mpwldectrl0, calib->p1_mpwldectrl0);
  402. MMDC1(mpwldectrl1, calib->p1_mpwldectrl1);
  403. MMDC1(mpdgctrl0, calib->p1_mpdgctrl0);
  404. MMDC1(mpdgctrl1, calib->p1_mpdgctrl1);
  405. MMDC1(mprddlctl, calib->p1_mprddlctl);
  406. MMDC1(mpwrdlctl, calib->p1_mpwrdlctl);
  407. }
  408. /* Read data DQ Byte0-3 delay */
  409. mmdc0->mprddqby0dl = 0x33333333;
  410. mmdc0->mprddqby1dl = 0x33333333;
  411. if (sysinfo->dsize > 0) {
  412. mmdc0->mprddqby2dl = 0x33333333;
  413. mmdc0->mprddqby3dl = 0x33333333;
  414. }
  415. if (sysinfo->dsize > 1) {
  416. MMDC1(mprddqby0dl, 0x33333333);
  417. MMDC1(mprddqby1dl, 0x33333333);
  418. MMDC1(mprddqby2dl, 0x33333333);
  419. MMDC1(mprddqby3dl, 0x33333333);
  420. }
  421. /* MMDC Termination: rtt_nom:2 RZQ/2(120ohm), rtt_nom:1 RZQ/4(60ohm) */
  422. val = (sysinfo->rtt_nom == 2) ? 0x00011117 : 0x00022227;
  423. mmdc0->mpodtctrl = val;
  424. if (sysinfo->dsize > 1)
  425. MMDC1(mpodtctrl, val);
  426. /* complete calibration */
  427. val = (1 << 11); /* Force measurement on delay-lines */
  428. mmdc0->mpmur0 = val;
  429. if (sysinfo->dsize > 1)
  430. MMDC1(mpmur0, val);
  431. /* Step 1: configuration request */
  432. mmdc0->mdscr = (u32)(1 << 15); /* config request */
  433. /* Step 2: Timing configuration */
  434. mmdc0->mdcfg0 = (trfc << 24) | (txs << 16) | (txp << 13) |
  435. (txpdll << 9) | (tfaw << 4) | tcl;
  436. mmdc0->mdcfg1 = (trcd << 29) | (trp << 26) | (trc << 21) |
  437. (tras << 16) | (1 << 15) /* trpa */ |
  438. (twr << 9) | (tmrd << 5) | tcwl;
  439. mmdc0->mdcfg2 = (tdllk << 16) | (trtp << 6) | (twtr << 3) | trrd;
  440. mmdc0->mdotc = (taofpd << 27) | (taonpd << 24) | (tanpd << 20) |
  441. (taxpd << 16) | (todtlon << 12) | (todt_idle_off << 4);
  442. mmdc0->mdasp = cs0_end; /* CS addressing */
  443. /* Step 3: Configure DDR type */
  444. mmdc0->mdmisc = (sysinfo->cs1_mirror << 19) | (sysinfo->walat << 16) |
  445. (sysinfo->bi_on << 12) | (sysinfo->mif3_mode << 9) |
  446. (sysinfo->ralat << 6);
  447. /* Step 4: Configure delay while leaving reset */
  448. mmdc0->mdor = (txpr << 16) | (sysinfo->sde_to_rst << 8) |
  449. (sysinfo->rst_to_cke << 0);
  450. /* Step 5: Configure DDR physical parameters (density and burst len) */
  451. coladdr = ddr3_cfg->coladdr;
  452. if (ddr3_cfg->coladdr == 8) /* 8-bit COL is 0x3 */
  453. coladdr += 4;
  454. else if (ddr3_cfg->coladdr == 12) /* 12-bit COL is 0x4 */
  455. coladdr += 1;
  456. mmdc0->mdctl = (ddr3_cfg->rowaddr - 11) << 24 | /* ROW */
  457. (coladdr - 9) << 20 | /* COL */
  458. (1 << 19) | /* Burst Length = 8 for DDR3 */
  459. (sysinfo->dsize << 16); /* DDR data bus size */
  460. /* Step 6: Perform ZQ calibration */
  461. val = 0xa1390001; /* one-time HW ZQ calib */
  462. mmdc0->mpzqhwctrl = val;
  463. if (sysinfo->dsize > 1)
  464. MMDC1(mpzqhwctrl, val);
  465. /* Step 7: Enable MMDC with desired chip select */
  466. mmdc0->mdctl |= (1 << 31) | /* SDE_0 for CS0 */
  467. ((sysinfo->ncs == 2) ? 1 : 0) << 30; /* SDE_1 for CS1 */
  468. /* Step 8: Write Mode Registers to Init DDR3 devices */
  469. for (cs = 0; cs < sysinfo->ncs; cs++) {
  470. /* MR2 */
  471. val = (sysinfo->rtt_wr & 3) << 9 | (ddr3_cfg->SRT & 1) << 7 |
  472. ((tcwl - 3) & 3) << 3;
  473. mmdc0->mdscr = MR(val, 2, 3, cs);
  474. /* MR3 */
  475. mmdc0->mdscr = MR(0, 3, 3, cs);
  476. /* MR1 */
  477. val = ((sysinfo->rtt_nom & 1) ? 1 : 0) << 2 |
  478. ((sysinfo->rtt_nom & 2) ? 1 : 0) << 6;
  479. mmdc0->mdscr = MR(val, 1, 3, cs);
  480. /* MR0 */
  481. val = ((tcl - 1) << 4) | /* CAS */
  482. (1 << 8) | /* DLL Reset */
  483. ((twr - 3) << 9); /* Write Recovery */
  484. mmdc0->mdscr = MR(val, 0, 3, cs);
  485. /* ZQ calibration */
  486. val = (1 << 10);
  487. mmdc0->mdscr = MR(val, 0, 4, cs);
  488. }
  489. /* Step 10: Power down control and self-refresh */
  490. mmdc0->mdpdc = (tcke & 0x7) << 16 |
  491. 5 << 12 | /* PWDT_1: 256 cycles */
  492. 5 << 8 | /* PWDT_0: 256 cycles */
  493. 1 << 7 | /* SLOW_PD */
  494. 1 << 6 | /* BOTH_CS_PD */
  495. (tcksrx & 0x7) << 3 |
  496. (tcksre & 0x7);
  497. mmdc0->mapsr = 0x00001006; /* ADOPT power down enabled */
  498. /* Step 11: Configure ZQ calibration: one-time and periodic 1ms */
  499. val = 0xa1390003;
  500. mmdc0->mpzqhwctrl = val;
  501. if (sysinfo->dsize > 1)
  502. MMDC1(mpzqhwctrl, val);
  503. /* Step 12: Configure and activate periodic refresh */
  504. mmdc0->mdref = (1 << 14) | /* REF_SEL: Periodic refresh cycle: 32kHz */
  505. (7 << 11); /* REFR: Refresh Rate - 8 refreshes */
  506. /* Step 13: Deassert config request - init complete */
  507. mmdc0->mdscr = 0x00000000;
  508. /* wait for auto-ZQ calibration to complete */
  509. mdelay(1);
  510. }