zynq-zc702.dts 6.3 KB

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  1. /*
  2. * Xilinx ZC702 board DTS
  3. *
  4. * Copyright (C) 2011 - 2015 Xilinx
  5. * Copyright (C) 2012 National Instruments Corp.
  6. *
  7. * SPDX-License-Identifier: GPL-2.0+
  8. */
  9. /dts-v1/;
  10. #include "zynq-7000.dtsi"
  11. / {
  12. model = "Zynq ZC702 Development Board";
  13. compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000";
  14. aliases {
  15. ethernet0 = &gem0;
  16. i2c0 = &i2c0;
  17. serial0 = &uart1;
  18. spi0 = &qspi;
  19. mmc0 = &sdhci0;
  20. };
  21. memory {
  22. device_type = "memory";
  23. reg = <0x0 0x40000000>;
  24. };
  25. chosen {
  26. bootargs = "earlyprintk";
  27. stdout-path = "serial0:115200n8";
  28. };
  29. gpio-keys {
  30. compatible = "gpio-keys";
  31. #address-cells = <1>;
  32. #size-cells = <0>;
  33. autorepeat;
  34. sw14 {
  35. label = "sw14";
  36. gpios = <&gpio0 12 0>;
  37. linux,code = <108>; /* down */
  38. gpio-key,wakeup;
  39. autorepeat;
  40. };
  41. sw13 {
  42. label = "sw13";
  43. gpios = <&gpio0 14 0>;
  44. linux,code = <103>; /* up */
  45. gpio-key,wakeup;
  46. autorepeat;
  47. };
  48. };
  49. leds {
  50. compatible = "gpio-leds";
  51. ds23 {
  52. label = "ds23";
  53. gpios = <&gpio0 10 0>;
  54. linux,default-trigger = "heartbeat";
  55. };
  56. };
  57. usb_phy0: phy0 {
  58. compatible = "usb-nop-xceiv";
  59. #phy-cells = <0>;
  60. };
  61. };
  62. &amba {
  63. ocm: sram@fffc0000 {
  64. compatible = "mmio-sram";
  65. reg = <0xfffc0000 0x10000>;
  66. };
  67. };
  68. &can0 {
  69. status = "okay";
  70. pinctrl-names = "default";
  71. pinctrl-0 = <&pinctrl_can0_default>;
  72. };
  73. &clkc {
  74. ps-clk-frequency = <33333333>;
  75. };
  76. &gem0 {
  77. status = "okay";
  78. phy-mode = "rgmii-id";
  79. phy-handle = <&ethernet_phy>;
  80. pinctrl-names = "default";
  81. pinctrl-0 = <&pinctrl_gem0_default>;
  82. ethernet_phy: ethernet-phy@7 {
  83. reg = <7>;
  84. };
  85. };
  86. &gpio0 {
  87. pinctrl-names = "default";
  88. pinctrl-0 = <&pinctrl_gpio0_default>;
  89. };
  90. &i2c0 {
  91. status = "okay";
  92. clock-frequency = <400000>;
  93. pinctrl-names = "default";
  94. pinctrl-0 = <&pinctrl_i2c0_default>;
  95. i2cswitch@74 {
  96. compatible = "nxp,pca9548";
  97. #address-cells = <1>;
  98. #size-cells = <0>;
  99. reg = <0x74>;
  100. i2c@0 {
  101. #address-cells = <1>;
  102. #size-cells = <0>;
  103. reg = <0>;
  104. si570: clock-generator@5d {
  105. #clock-cells = <0>;
  106. compatible = "silabs,si570";
  107. temperature-stability = <50>;
  108. reg = <0x5d>;
  109. factory-fout = <156250000>;
  110. clock-frequency = <148500000>;
  111. };
  112. };
  113. i2c@2 {
  114. #address-cells = <1>;
  115. #size-cells = <0>;
  116. reg = <2>;
  117. eeprom@54 {
  118. compatible = "at,24c08";
  119. reg = <0x54>;
  120. };
  121. };
  122. i2c@3 {
  123. #address-cells = <1>;
  124. #size-cells = <0>;
  125. reg = <3>;
  126. gpio@21 {
  127. compatible = "ti,tca6416";
  128. reg = <0x21>;
  129. gpio-controller;
  130. #gpio-cells = <2>;
  131. };
  132. };
  133. i2c@4 {
  134. #address-cells = <1>;
  135. #size-cells = <0>;
  136. reg = <4>;
  137. rtc@51 {
  138. compatible = "nxp,pcf8563";
  139. reg = <0x51>;
  140. };
  141. };
  142. i2c@7 {
  143. #address-cells = <1>;
  144. #size-cells = <0>;
  145. reg = <7>;
  146. hwmon@52 {
  147. compatible = "ti,ucd9248";
  148. reg = <52>;
  149. };
  150. hwmon@53 {
  151. compatible = "ti,ucd9248";
  152. reg = <53>;
  153. };
  154. hwmon@54 {
  155. compatible = "ti,ucd9248";
  156. reg = <54>;
  157. };
  158. };
  159. };
  160. };
  161. &pinctrl0 {
  162. pinctrl_can0_default: can0-default {
  163. mux {
  164. function = "can0";
  165. groups = "can0_9_grp";
  166. };
  167. conf {
  168. groups = "can0_9_grp";
  169. slew-rate = <0>;
  170. io-standard = <1>;
  171. };
  172. conf-rx {
  173. pins = "MIO46";
  174. bias-high-impedance;
  175. };
  176. conf-tx {
  177. pins = "MIO47";
  178. bias-disable;
  179. };
  180. };
  181. pinctrl_gem0_default: gem0-default {
  182. mux {
  183. function = "ethernet0";
  184. groups = "ethernet0_0_grp";
  185. };
  186. conf {
  187. groups = "ethernet0_0_grp";
  188. slew-rate = <0>;
  189. io-standard = <4>;
  190. };
  191. conf-rx {
  192. pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27";
  193. bias-high-impedance;
  194. low-power-disable;
  195. };
  196. conf-tx {
  197. pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21";
  198. bias-disable;
  199. low-power-enable;
  200. };
  201. mux-mdio {
  202. function = "mdio0";
  203. groups = "mdio0_0_grp";
  204. };
  205. conf-mdio {
  206. groups = "mdio0_0_grp";
  207. slew-rate = <0>;
  208. io-standard = <1>;
  209. bias-disable;
  210. };
  211. };
  212. pinctrl_gpio0_default: gpio0-default {
  213. mux {
  214. function = "gpio0";
  215. groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp",
  216. "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp",
  217. "gpio0_13_grp", "gpio0_14_grp";
  218. };
  219. conf {
  220. groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp",
  221. "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp",
  222. "gpio0_13_grp", "gpio0_14_grp";
  223. slew-rate = <0>;
  224. io-standard = <1>;
  225. };
  226. conf-pull-up {
  227. pins = "MIO9", "MIO10", "MIO11", "MIO12", "MIO13", "MIO14";
  228. bias-pull-up;
  229. };
  230. conf-pull-none {
  231. pins = "MIO7", "MIO8";
  232. bias-disable;
  233. };
  234. };
  235. pinctrl_i2c0_default: i2c0-default {
  236. mux {
  237. groups = "i2c0_10_grp";
  238. function = "i2c0";
  239. };
  240. conf {
  241. groups = "i2c0_10_grp";
  242. bias-pull-up;
  243. slew-rate = <0>;
  244. io-standard = <1>;
  245. };
  246. };
  247. pinctrl_sdhci0_default: sdhci0-default {
  248. mux {
  249. groups = "sdio0_2_grp";
  250. function = "sdio0";
  251. };
  252. conf {
  253. groups = "sdio0_2_grp";
  254. slew-rate = <0>;
  255. io-standard = <1>;
  256. bias-disable;
  257. };
  258. mux-cd {
  259. groups = "gpio0_0_grp";
  260. function = "sdio0_cd";
  261. };
  262. conf-cd {
  263. groups = "gpio0_0_grp";
  264. bias-high-impedance;
  265. bias-pull-up;
  266. slew-rate = <0>;
  267. io-standard = <1>;
  268. };
  269. mux-wp {
  270. groups = "gpio0_15_grp";
  271. function = "sdio0_wp";
  272. };
  273. conf-wp {
  274. groups = "gpio0_15_grp";
  275. bias-high-impedance;
  276. bias-pull-up;
  277. slew-rate = <0>;
  278. io-standard = <1>;
  279. };
  280. };
  281. pinctrl_uart1_default: uart1-default {
  282. mux {
  283. groups = "uart1_10_grp";
  284. function = "uart1";
  285. };
  286. conf {
  287. groups = "uart1_10_grp";
  288. slew-rate = <0>;
  289. io-standard = <1>;
  290. };
  291. conf-rx {
  292. pins = "MIO49";
  293. bias-high-impedance;
  294. };
  295. conf-tx {
  296. pins = "MIO48";
  297. bias-disable;
  298. };
  299. };
  300. pinctrl_usb0_default: usb0-default {
  301. mux {
  302. groups = "usb0_0_grp";
  303. function = "usb0";
  304. };
  305. conf {
  306. groups = "usb0_0_grp";
  307. slew-rate = <0>;
  308. io-standard = <1>;
  309. };
  310. conf-rx {
  311. pins = "MIO29", "MIO31", "MIO36";
  312. bias-high-impedance;
  313. };
  314. conf-tx {
  315. pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34",
  316. "MIO35", "MIO37", "MIO38", "MIO39";
  317. bias-disable;
  318. };
  319. };
  320. };
  321. &sdhci0 {
  322. u-boot,dm-pre-reloc;
  323. status = "okay";
  324. pinctrl-names = "default";
  325. pinctrl-0 = <&pinctrl_sdhci0_default>;
  326. };
  327. &uart1 {
  328. u-boot,dm-pre-reloc;
  329. status = "okay";
  330. pinctrl-names = "default";
  331. pinctrl-0 = <&pinctrl_uart1_default>;
  332. };
  333. &qspi {
  334. u-boot,dm-pre-reloc;
  335. status = "okay";
  336. };
  337. &usb0 {
  338. status = "okay";
  339. dr_mode = "host";
  340. usb-phy = <&usb_phy0>;
  341. pinctrl-names = "default";
  342. pinctrl-0 = <&pinctrl_usb0_default>;
  343. };