ddr3_k2e.c 1.1 KB

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  1. /*
  2. * Keystone2: DDR3 initialization
  3. *
  4. * (C) Copyright 2014-2015
  5. * Texas Instruments Incorporated, <www.ti.com>
  6. *
  7. * SPDX-License-Identifier: GPL-2.0+
  8. */
  9. #include <common.h>
  10. #include "ddr3_cfg.h"
  11. #include <asm/arch/ddr3.h>
  12. static struct pll_init_data ddr3_400 = DDR3_PLL_400;
  13. static struct pll_init_data ddr3_333 = DDR3_PLL_333;
  14. u32 ddr3_init(void)
  15. {
  16. struct ddr3_spd_cb spd_cb;
  17. if (ddr3_get_dimm_params_from_spd(&spd_cb)) {
  18. printf("Sorry, I don't know how to configure DDR3A.\n"
  19. "Bye :(\n");
  20. for (;;)
  21. ;
  22. }
  23. printf("Detected SO-DIMM [%s]\n", spd_cb.dimm_name);
  24. printf("DDR3 speed %d\n", spd_cb.ddrspdclock);
  25. if (spd_cb.ddrspdclock == 1600)
  26. init_pll(&ddr3_400);
  27. else
  28. init_pll(&ddr3_333);
  29. /* Reset DDR3 PHY after PLL enabled */
  30. ddr3_reset_ddrphy();
  31. spd_cb.phy_cfg.zq0cr1 |= 0x10000;
  32. spd_cb.phy_cfg.zq1cr1 |= 0x10000;
  33. spd_cb.phy_cfg.zq2cr1 |= 0x10000;
  34. ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &spd_cb.phy_cfg);
  35. ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &spd_cb.emif_cfg);
  36. printf("DRAM: %d GiB\n", spd_cb.ddr_size_gbyte);
  37. return (u32)spd_cb.ddr_size_gbyte;
  38. }