ddr3_cfg.c 1.4 KB

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  1. /*
  2. * Keystone2: DDR3 configuration
  3. *
  4. * (C) Copyright 2012-2014
  5. * Texas Instruments Incorporated, <www.ti.com>
  6. *
  7. * SPDX-License-Identifier: GPL-2.0+
  8. */
  9. #include <common.h>
  10. #include <asm/arch/ddr3.h>
  11. #include "ddr3_cfg.h"
  12. struct ddr3_phy_config ddr3phy_1600_2g = {
  13. .pllcr = 0x0001C000ul,
  14. .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
  15. .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
  16. .ptr0 = 0x42C21590ul,
  17. .ptr1 = 0xD05612C0ul,
  18. .ptr2 = 0, /* not set in gel */
  19. .ptr3 = 0x0D861A80ul,
  20. .ptr4 = 0x0C827100ul,
  21. .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
  22. .dcr_val = ((1 << 10)),
  23. .dtpr0 = 0x9D5CBB66ul,
  24. .dtpr1 = 0x12868300ul,
  25. .dtpr2 = 0x5002D200ul,
  26. .mr0 = 0x00001C70ul,
  27. .mr1 = 0x00000006ul,
  28. .mr2 = 0x00000018ul,
  29. .dtcr = 0x710035C7ul,
  30. .pgcr2 = 0x00F07A12ul,
  31. .zq0cr1 = 0x0001005Dul,
  32. .zq1cr1 = 0x0001005Bul,
  33. .zq2cr1 = 0x0001005Bul,
  34. .pir_v1 = 0x00000033ul,
  35. .pir_v2 = 0x0000FF81ul,
  36. };
  37. struct ddr3_emif_config ddr3_1600_2g = {
  38. .sdcfg = 0x6200CE62ul,
  39. .sdtim1 = 0x166C9855ul,
  40. .sdtim2 = 0x00001D4Aul,
  41. .sdtim3 = 0x435DFF53ul,
  42. .sdtim4 = 0x543F0CFFul,
  43. .zqcfg = 0x70073200ul,
  44. .sdrfc = 0x00001869ul,
  45. };