rk_pwm.c 2.4 KB

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  1. /*
  2. * Copyright (c) 2016 Google, Inc
  3. * Written by Simon Glass <sjg@chromium.org>
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. #include <common.h>
  8. #include <div64.h>
  9. #include <dm.h>
  10. #include <pwm.h>
  11. #include <regmap.h>
  12. #include <syscon.h>
  13. #include <asm/io.h>
  14. #include <asm/arch/clock.h>
  15. #include <asm/arch/cru_rk3288.h>
  16. #include <asm/arch/grf_rk3288.h>
  17. #include <asm/arch/pwm.h>
  18. #include <power/regulator.h>
  19. DECLARE_GLOBAL_DATA_PTR;
  20. struct rk_pwm_priv {
  21. struct rk3288_pwm *regs;
  22. struct rk3288_grf *grf;
  23. };
  24. static int rk_pwm_set_config(struct udevice *dev, uint channel, uint period_ns,
  25. uint duty_ns)
  26. {
  27. struct rk_pwm_priv *priv = dev_get_priv(dev);
  28. struct rk3288_pwm *regs = priv->regs;
  29. unsigned long period, duty;
  30. debug("%s: period_ns=%u, duty_ns=%u\n", __func__, period_ns, duty_ns);
  31. writel(PWM_SEL_SRC_CLK | PWM_OUTPUT_LEFT | PWM_LP_DISABLE |
  32. PWM_CONTINUOUS | PWM_DUTY_POSTIVE | PWM_INACTIVE_POSTIVE |
  33. RK_PWM_DISABLE,
  34. &regs->ctrl);
  35. period = lldiv((uint64_t)(PD_BUS_PCLK_HZ / 1000) * period_ns, 1000000);
  36. duty = lldiv((uint64_t)(PD_BUS_PCLK_HZ / 1000) * duty_ns, 1000000);
  37. writel(period, &regs->period_hpr);
  38. writel(duty, &regs->duty_lpr);
  39. debug("%s: period=%lu, duty=%lu\n", __func__, period, duty);
  40. return 0;
  41. }
  42. static int rk_pwm_set_enable(struct udevice *dev, uint channel, bool enable)
  43. {
  44. struct rk_pwm_priv *priv = dev_get_priv(dev);
  45. struct rk3288_pwm *regs = priv->regs;
  46. debug("%s: Enable '%s'\n", __func__, dev->name);
  47. clrsetbits_le32(&regs->ctrl, RK_PWM_ENABLE, enable ? RK_PWM_ENABLE : 0);
  48. return 0;
  49. }
  50. static int rk_pwm_ofdata_to_platdata(struct udevice *dev)
  51. {
  52. struct rk_pwm_priv *priv = dev_get_priv(dev);
  53. struct regmap *map;
  54. priv->regs = (struct rk3288_pwm *)dev_get_addr(dev);
  55. map = syscon_get_regmap_by_driver_data(ROCKCHIP_SYSCON_GRF);
  56. if (IS_ERR(map))
  57. return PTR_ERR(map);
  58. priv->grf = regmap_get_range(map, 0);
  59. return 0;
  60. }
  61. static int rk_pwm_probe(struct udevice *dev)
  62. {
  63. struct rk_pwm_priv *priv = dev_get_priv(dev);
  64. rk_setreg(&priv->grf->soc_con2, 1 << 0);
  65. return 0;
  66. }
  67. static const struct pwm_ops rk_pwm_ops = {
  68. .set_config = rk_pwm_set_config,
  69. .set_enable = rk_pwm_set_enable,
  70. };
  71. static const struct udevice_id rk_pwm_ids[] = {
  72. { .compatible = "rockchip,rk3288-pwm" },
  73. { }
  74. };
  75. U_BOOT_DRIVER(rk_pwm) = {
  76. .name = "rk_pwm",
  77. .id = UCLASS_PWM,
  78. .of_match = rk_pwm_ids,
  79. .ops = &rk_pwm_ops,
  80. .ofdata_to_platdata = rk_pwm_ofdata_to_platdata,
  81. .probe = rk_pwm_probe,
  82. .priv_auto_alloc_size = sizeof(struct rk_pwm_priv),
  83. };