boot.c 2.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * OMAP4 boot
  4. *
  5. * Copyright (C) 2015 Paul Kocialkowski <contact@paulk.fr>
  6. */
  7. #include <common.h>
  8. #include <asm/io.h>
  9. #include <asm/omap_common.h>
  10. #include <asm/arch/sys_proto.h>
  11. #include <spl.h>
  12. static u32 boot_devices[] = {
  13. BOOT_DEVICE_MMC2,
  14. BOOT_DEVICE_XIP,
  15. BOOT_DEVICE_XIPWAIT,
  16. BOOT_DEVICE_NAND,
  17. BOOT_DEVICE_XIPWAIT,
  18. BOOT_DEVICE_MMC1,
  19. BOOT_DEVICE_ONENAND,
  20. BOOT_DEVICE_ONENAND,
  21. BOOT_DEVICE_MMC2,
  22. BOOT_DEVICE_ONENAND,
  23. BOOT_DEVICE_XIPWAIT,
  24. BOOT_DEVICE_NAND,
  25. BOOT_DEVICE_NAND,
  26. BOOT_DEVICE_MMC1,
  27. BOOT_DEVICE_ONENAND,
  28. BOOT_DEVICE_MMC2,
  29. BOOT_DEVICE_XIP,
  30. BOOT_DEVICE_XIPWAIT,
  31. BOOT_DEVICE_NAND,
  32. BOOT_DEVICE_MMC1,
  33. BOOT_DEVICE_MMC1,
  34. BOOT_DEVICE_ONENAND,
  35. BOOT_DEVICE_MMC2,
  36. BOOT_DEVICE_XIP,
  37. BOOT_DEVICE_MMC2_2,
  38. BOOT_DEVICE_NAND,
  39. BOOT_DEVICE_MMC2_2,
  40. BOOT_DEVICE_MMC1,
  41. BOOT_DEVICE_MMC2_2,
  42. BOOT_DEVICE_MMC2_2,
  43. BOOT_DEVICE_NONE,
  44. BOOT_DEVICE_XIPWAIT,
  45. };
  46. u32 omap_sys_boot_device(void)
  47. {
  48. u32 sys_boot;
  49. /* Grab the first 5 bits of the status register for SYS_BOOT. */
  50. sys_boot = readl((u32 *) (*ctrl)->control_status) & ((1 << 5) - 1);
  51. if (sys_boot >= (sizeof(boot_devices) / sizeof(u32)))
  52. return BOOT_DEVICE_NONE;
  53. return boot_devices[sys_boot];
  54. }
  55. int omap_reboot_mode(char *mode, unsigned int length)
  56. {
  57. unsigned int limit;
  58. unsigned int i;
  59. if (length < 2)
  60. return -1;
  61. if (!warm_reset())
  62. return -1;
  63. limit = (length < OMAP_REBOOT_REASON_SIZE) ? length :
  64. OMAP_REBOOT_REASON_SIZE;
  65. for (i = 0; i < (limit - 1); i++)
  66. mode[i] = readb((u8 *)(OMAP44XX_SAR_RAM_BASE +
  67. OMAP_REBOOT_REASON_OFFSET + i));
  68. mode[i] = '\0';
  69. return 0;
  70. }
  71. int omap_reboot_mode_clear(void)
  72. {
  73. writeb(0, (u8 *)(OMAP44XX_SAR_RAM_BASE + OMAP_REBOOT_REASON_OFFSET));
  74. return 0;
  75. }
  76. int omap_reboot_mode_store(char *mode)
  77. {
  78. unsigned int i;
  79. for (i = 0; i < (OMAP_REBOOT_REASON_SIZE - 1) && mode[i] != '\0'; i++)
  80. writeb(mode[i], (u8 *)(OMAP44XX_SAR_RAM_BASE +
  81. OMAP_REBOOT_REASON_OFFSET + i));
  82. writeb('\0', (u8 *)(OMAP44XX_SAR_RAM_BASE +
  83. OMAP_REBOOT_REASON_OFFSET + i));
  84. return 0;
  85. }