omap.h 3.6 KB

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  1. /*
  2. * (C) Copyright 2010
  3. * Texas Instruments, <www.ti.com>
  4. *
  5. * Authors:
  6. * Aneesh V <aneesh@ti.com>
  7. *
  8. * Derived from OMAP3 work by
  9. * Richard Woodruff <r-woodruff2@ti.com>
  10. * Syed Mohammed Khasim <x0khasim@ti.com>
  11. *
  12. * SPDX-License-Identifier: GPL-2.0+
  13. */
  14. #ifndef _OMAP4_H_
  15. #define _OMAP4_H_
  16. #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
  17. #include <asm/types.h>
  18. #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
  19. /*
  20. * L4 Peripherals - L4 Wakeup and L4 Core now
  21. */
  22. #define OMAP44XX_L4_CORE_BASE 0x4A000000
  23. #define OMAP44XX_L4_WKUP_BASE 0x4A300000
  24. #define OMAP44XX_L4_PER_BASE 0x48000000
  25. #define OMAP44XX_DRAM_ADDR_SPACE_START 0x80000000
  26. #define OMAP44XX_DRAM_ADDR_SPACE_END 0xD0000000
  27. #define DRAM_ADDR_SPACE_START OMAP44XX_DRAM_ADDR_SPACE_START
  28. #define DRAM_ADDR_SPACE_END OMAP44XX_DRAM_ADDR_SPACE_END
  29. /* CONTROL_ID_CODE */
  30. #define CONTROL_ID_CODE 0x4A002204
  31. #define STD_FUSE_DIE_ID_0 0x4A002200
  32. #define STD_FUSE_DIE_ID_1 0x4A002208
  33. #define STD_FUSE_DIE_ID_2 0x4A00220c
  34. #define STD_FUSE_DIE_ID_3 0x4A002210
  35. #define OMAP4_CONTROL_ID_CODE_ES1_0 0x0B85202F
  36. #define OMAP4_CONTROL_ID_CODE_ES2_0 0x1B85202F
  37. #define OMAP4_CONTROL_ID_CODE_ES2_1 0x3B95C02F
  38. #define OMAP4_CONTROL_ID_CODE_ES2_2 0x4B95C02F
  39. #define OMAP4_CONTROL_ID_CODE_ES2_3 0x6B95C02F
  40. #define OMAP4460_CONTROL_ID_CODE_ES1_0 0x0B94E02F
  41. #define OMAP4460_CONTROL_ID_CODE_ES1_1 0x2B94E02F
  42. #define OMAP4470_CONTROL_ID_CODE_ES1_0 0x0B97502F
  43. /* UART */
  44. #define UART1_BASE (OMAP44XX_L4_PER_BASE + 0x6a000)
  45. #define UART2_BASE (OMAP44XX_L4_PER_BASE + 0x6c000)
  46. #define UART3_BASE (OMAP44XX_L4_PER_BASE + 0x20000)
  47. /* General Purpose Timers */
  48. #define GPT1_BASE (OMAP44XX_L4_WKUP_BASE + 0x18000)
  49. #define GPT2_BASE (OMAP44XX_L4_PER_BASE + 0x32000)
  50. #define GPT3_BASE (OMAP44XX_L4_PER_BASE + 0x34000)
  51. /* Watchdog Timer2 - MPU watchdog */
  52. #define WDT2_BASE (OMAP44XX_L4_WKUP_BASE + 0x14000)
  53. /* GPMC */
  54. #define OMAP44XX_GPMC_BASE 0x50000000
  55. /*
  56. * Hardware Register Details
  57. */
  58. /* Watchdog Timer */
  59. #define WD_UNLOCK1 0xAAAA
  60. #define WD_UNLOCK2 0x5555
  61. /* GP Timer */
  62. #define TCLR_ST (0x1 << 0)
  63. #define TCLR_AR (0x1 << 1)
  64. #define TCLR_PRE (0x1 << 5)
  65. /* Control Module */
  66. #define LDOSRAM_ACTMODE_VSET_IN_MASK (0x1F << 5)
  67. #define LDOSRAM_VOLT_CTRL_OVERRIDE 0x0401040f
  68. #define CONTROL_EFUSE_1_OVERRIDE 0x1C4D0110
  69. #define CONTROL_EFUSE_2_OVERRIDE 0x99084000
  70. /* LPDDR2 IO regs */
  71. #define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN 0x1C1C1C1C
  72. #define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER 0x9E9E9E9E
  73. #define CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN 0x7C7C7C7C
  74. #define LPDDR2IO_GR10_WD_MASK (3 << 17)
  75. #define CONTROL_LPDDR2IO_3_VAL 0xA0888C0F
  76. /* CONTROL_EFUSE_2 */
  77. #define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000
  78. #define MMC1_PWRDNZ (1 << 26)
  79. #define MMC1_PBIASLITE_PWRDNZ (1 << 22)
  80. #define MMC1_PBIASLITE_VMODE (1 << 21)
  81. #ifndef __ASSEMBLY__
  82. struct s32ktimer {
  83. unsigned char res[0x10];
  84. unsigned int s32k_cr; /* 0x10 */
  85. };
  86. #define DEVICE_TYPE_SHIFT (0x8)
  87. #define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT)
  88. #define DEVICE_GP 0x3
  89. #endif /* __ASSEMBLY__ */
  90. /*
  91. * Non-secure SRAM Addresses
  92. * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE
  93. * at 0x40304000(EMU base) so that our code works for both EMU and GP
  94. */
  95. #define NON_SECURE_SRAM_START 0x40304000
  96. #define NON_SECURE_SRAM_END 0x4030E000 /* Not inclusive */
  97. #define SRAM_SCRATCH_SPACE_ADDR 0x4030C000
  98. /* base address for indirect vectors (internal boot mode) */
  99. #define SRAM_ROM_VECT_BASE 0x4030D000
  100. /* ABB settings */
  101. #define OMAP_ABB_SETTLING_TIME 50
  102. #define OMAP_ABB_CLOCK_CYCLES 16
  103. /* ABB tranxdone mask */
  104. #define OMAP_ABB_MPU_TXDONE_MASK (0x1 << 7)
  105. #endif