mem.h 14 KB

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  1. /*
  2. * (C) Copyright 2006-2008
  3. * Texas Instruments, <www.ti.com>
  4. * Richard Woodruff <r-woodruff2@ti.com>
  5. *
  6. * SPDX-License-Identifier: GPL-2.0+
  7. */
  8. #ifndef _MEM_H_
  9. #define _MEM_H_
  10. #define CS0 0x0
  11. #define CS1 0x1 /* mirror CS1 regs appear offset 0x30 from CS0 */
  12. #ifndef __ASSEMBLY__
  13. enum {
  14. STACKED = 0,
  15. IP_DDR = 1,
  16. COMBO_DDR = 2,
  17. IP_SDR = 3,
  18. };
  19. #endif /* __ASSEMBLY__ */
  20. #define EARLY_INIT 1
  21. /*
  22. * For a full explanation of these registers and values please see
  23. * the Technical Reference Manual (TRM) for any of the processors in
  24. * this family.
  25. */
  26. /* Slower full frequency range default timings for x32 operation*/
  27. #define SDRC_SHARING 0x00000100
  28. #define SDRC_MR_0_SDR 0x00000031
  29. /*
  30. * SDRC autorefresh control values. This register consists of autorefresh
  31. * enable at bits 0:1 and an autorefresh counter value in bits 8:23. The
  32. * counter is a result of ( tREFI / tCK ) - 50.
  33. */
  34. #define SDP_3430_SDRC_RFR_CTRL_100MHz 0x0002da01
  35. #define SDP_3430_SDRC_RFR_CTRL_133MHz 0x0003de01 /* 7.8us/7.5ns - 50=0x3de */
  36. #define SDP_3430_SDRC_RFR_CTRL_165MHz 0x0004e201 /* 7.8us/6ns - 50=0x4e2 */
  37. #define SDP_3430_SDRC_RFR_CTRL_200MHz 0x0005e601 /* 7.8us/5ns - 50=0x5e6 */
  38. #define DLL_OFFSET 0
  39. #define DLL_WRITEDDRCLKX2DIS 1
  40. #define DLL_ENADLL 1
  41. #define DLL_LOCKDLL 0
  42. #define DLL_DLLPHASE_72 0
  43. #define DLL_DLLPHASE_90 1
  44. /* rkw - need to find of 90/72 degree recommendation for speed like before */
  45. #define SDP_SDRC_DLLAB_CTRL ((DLL_ENADLL << 3) | \
  46. (DLL_LOCKDLL << 2) | (DLL_DLLPHASE_90 << 1))
  47. /* Helper macros to arrive at value of the SDRC_ACTIM_CTRLA register. */
  48. #define ACTIM_CTRLA_TRFC(v) (((v) & 0x1F) << 27) /* 31:27 */
  49. #define ACTIM_CTRLA_TRC(v) (((v) & 0x1F) << 22) /* 26:22 */
  50. #define ACTIM_CTRLA_TRAS(v) (((v) & 0x0F) << 18) /* 21:18 */
  51. #define ACTIM_CTRLA_TRP(v) (((v) & 0x07) << 15) /* 17:15 */
  52. #define ACTIM_CTRLA_TRCD(v) (((v) & 0x07) << 12) /* 14:12 */
  53. #define ACTIM_CTRLA_TRRD(v) (((v) & 0x07) << 9) /* 11:9 */
  54. #define ACTIM_CTRLA_TDPL(v) (((v) & 0x07) << 6) /* 8:6 */
  55. #define ACTIM_CTRLA_TDAL(v) (v & 0x1F) /* 4:0 */
  56. #define ACTIM_CTRLA(trfc, trc, tras, trp, trcd, trrd, tdpl, tdal) \
  57. ACTIM_CTRLA_TRFC(trfc) | \
  58. ACTIM_CTRLA_TRC(trc) | \
  59. ACTIM_CTRLA_TRAS(tras) | \
  60. ACTIM_CTRLA_TRP(trp) | \
  61. ACTIM_CTRLA_TRCD(trcd) | \
  62. ACTIM_CTRLA_TRRD(trrd) | \
  63. ACTIM_CTRLA_TDPL(tdpl) | \
  64. ACTIM_CTRLA_TDAL(tdal)
  65. /* Helper macros to arrive at value of the SDRC_ACTIM_CTRLB register. */
  66. #define ACTIM_CTRLB_TWTR(v) (((v) & 0x03) << 16) /* 17:16 */
  67. #define ACTIM_CTRLB_TCKE(v) (((v) & 0x07) << 12) /* 14:12 */
  68. #define ACTIM_CTRLB_TXP(v) (((v) & 0x07) << 8) /* 10:8 */
  69. #define ACTIM_CTRLB_TXSR(v) (v & 0xFF) /* 7:0 */
  70. #define ACTIM_CTRLB(twtr, tcke, txp, txsr) \
  71. ACTIM_CTRLB_TWTR(twtr) | \
  72. ACTIM_CTRLB_TCKE(tcke) | \
  73. ACTIM_CTRLB_TXP(txp) | \
  74. ACTIM_CTRLB_TXSR(txsr)
  75. /*
  76. * Values used in the MCFG register. Only values we use today
  77. * are defined and the rest can be found in the TRM. Unless otherwise
  78. * noted all fields are one bit.
  79. */
  80. #define V_MCFG_RAMTYPE_DDR (0x1)
  81. #define V_MCFG_DEEPPD_EN (0x1 << 3)
  82. #define V_MCFG_B32NOT16_32 (0x1 << 4)
  83. #define V_MCFG_BANKALLOCATION_RBC (0x2 << 6) /* 6:7 */
  84. #define V_MCFG_RAMSIZE(ramsize) ((((ramsize) >> 20)/2) << 8) /* 8:17 */
  85. #define V_MCFG_ADDRMUXLEGACY_FLEX (0x1 << 19)
  86. #define V_MCFG_CASWIDTH(caswidth) (((caswidth)-5) << 20) /* 20:22 */
  87. #define V_MCFG_CASWIDTH_10B V_MCFG_CASWIDTH(10)
  88. #define V_MCFG_RASWIDTH(raswidth) (((raswidth)-11) << 24) /* 24:26 */
  89. /* Macro to construct MCFG */
  90. #define MCFG(ramsize, raswidth) \
  91. V_MCFG_RASWIDTH(raswidth) | V_MCFG_CASWIDTH_10B | \
  92. V_MCFG_ADDRMUXLEGACY_FLEX | V_MCFG_RAMSIZE(ramsize) | \
  93. V_MCFG_BANKALLOCATION_RBC | V_MCFG_B32NOT16_32 | \
  94. V_MCFG_DEEPPD_EN | V_MCFG_RAMTYPE_DDR
  95. /* Hynix part of Overo (165MHz optimized) 6.06ns */
  96. #define HYNIX_TDAL_165 6
  97. #define HYNIX_TDPL_165 3
  98. #define HYNIX_TRRD_165 2
  99. #define HYNIX_TRCD_165 3
  100. #define HYNIX_TRP_165 3
  101. #define HYNIX_TRAS_165 7
  102. #define HYNIX_TRC_165 10
  103. #define HYNIX_TRFC_165 21
  104. #define HYNIX_V_ACTIMA_165 \
  105. ACTIM_CTRLA(HYNIX_TRFC_165, HYNIX_TRC_165, \
  106. HYNIX_TRAS_165, HYNIX_TRP_165, \
  107. HYNIX_TRCD_165, HYNIX_TRRD_165, \
  108. HYNIX_TDPL_165, HYNIX_TDAL_165)
  109. #define HYNIX_TWTR_165 1
  110. #define HYNIX_TCKE_165 1
  111. #define HYNIX_TXP_165 2
  112. #define HYNIX_XSR_165 24
  113. #define HYNIX_V_ACTIMB_165 \
  114. ACTIM_CTRLB(HYNIX_TWTR_165, HYNIX_TCKE_165, \
  115. HYNIX_TXP_165, HYNIX_XSR_165)
  116. #define HYNIX_RASWIDTH_165 13
  117. #define HYNIX_V_MCFG_165(size) MCFG((size), HYNIX_RASWIDTH_165)
  118. /* Hynix part of AM/DM37xEVM (200MHz optimized) */
  119. #define HYNIX_TDAL_200 6
  120. #define HYNIX_TDPL_200 3
  121. #define HYNIX_TRRD_200 2
  122. #define HYNIX_TRCD_200 4
  123. #define HYNIX_TRP_200 3
  124. #define HYNIX_TRAS_200 8
  125. #define HYNIX_TRC_200 11
  126. #define HYNIX_TRFC_200 18
  127. #define HYNIX_V_ACTIMA_200 \
  128. ACTIM_CTRLA(HYNIX_TRFC_200, HYNIX_TRC_200, \
  129. HYNIX_TRAS_200, HYNIX_TRP_200, \
  130. HYNIX_TRCD_200, HYNIX_TRRD_200, \
  131. HYNIX_TDPL_200, HYNIX_TDAL_200)
  132. #define HYNIX_TWTR_200 2
  133. #define HYNIX_TCKE_200 1
  134. #define HYNIX_TXP_200 1
  135. #define HYNIX_XSR_200 28
  136. #define HYNIX_V_ACTIMB_200 \
  137. ACTIM_CTRLB(HYNIX_TWTR_200, HYNIX_TCKE_200, \
  138. HYNIX_TXP_200, HYNIX_XSR_200)
  139. #define HYNIX_RASWIDTH_200 14
  140. #define HYNIX_V_MCFG_200(size) MCFG((size), HYNIX_RASWIDTH_200)
  141. /* Infineon part of 3430SDP (165MHz optimized) 6.06ns */
  142. #define INFINEON_TDAL_165 6 /* Twr/Tck + Trp/tck */
  143. /* 15/6 + 18/6 = 5.5 -> 6 */
  144. #define INFINEON_TDPL_165 3 /* 15/6 = 2.5 -> 3 (Twr) */
  145. #define INFINEON_TRRD_165 2 /* 12/6 = 2 */
  146. #define INFINEON_TRCD_165 3 /* 18/6 = 3 */
  147. #define INFINEON_TRP_165 3 /* 18/6 = 3 */
  148. #define INFINEON_TRAS_165 7 /* 42/6 = 7 */
  149. #define INFINEON_TRC_165 10 /* 60/6 = 10 */
  150. #define INFINEON_TRFC_165 12 /* 72/6 = 12 */
  151. #define INFINEON_V_ACTIMA_165 \
  152. ACTIM_CTRLA(INFINEON_TRFC_165, INFINEON_TRC_165, \
  153. INFINEON_TRAS_165, INFINEON_TRP_165, \
  154. INFINEON_TRCD_165, INFINEON_TRRD_165, \
  155. INFINEON_TDPL_165, INFINEON_TDAL_165)
  156. #define INFINEON_TWTR_165 1
  157. #define INFINEON_TCKE_165 2
  158. #define INFINEON_TXP_165 2
  159. #define INFINEON_XSR_165 20 /* 120/6 = 20 */
  160. #define INFINEON_V_ACTIMB_165 \
  161. ACTIM_CTRLB(INFINEON_TWTR_165, INFINEON_TCKE_165, \
  162. INFINEON_TXP_165, INFINEON_XSR_165)
  163. /* Micron part of 3430 EVM (165MHz optimized) 6.06ns */
  164. #define MICRON_TDAL_165 6 /* Twr/Tck + Trp/tck */
  165. /* 15/6 + 18/6 = 5.5 -> 6 */
  166. #define MICRON_TDPL_165 3 /* 15/6 = 2.5 -> 3 (Twr) */
  167. #define MICRON_TRRD_165 2 /* 12/6 = 2 */
  168. #define MICRON_TRCD_165 3 /* 18/6 = 3 */
  169. #define MICRON_TRP_165 3 /* 18/6 = 3 */
  170. #define MICRON_TRAS_165 7 /* 42/6 = 7 */
  171. #define MICRON_TRC_165 10 /* 60/6 = 10 */
  172. #define MICRON_TRFC_165 21 /* 125/6 = 21 */
  173. #define MICRON_V_ACTIMA_165 \
  174. ACTIM_CTRLA(MICRON_TRFC_165, MICRON_TRC_165, \
  175. MICRON_TRAS_165, MICRON_TRP_165, \
  176. MICRON_TRCD_165, MICRON_TRRD_165, \
  177. MICRON_TDPL_165, MICRON_TDAL_165)
  178. #define MICRON_TWTR_165 1
  179. #define MICRON_TCKE_165 1
  180. #define MICRON_XSR_165 23 /* 138/6 = 23 */
  181. #define MICRON_TXP_165 5 /* 25/6 = 4.1 => ~5 */
  182. #define MICRON_V_ACTIMB_165 \
  183. ACTIM_CTRLB(MICRON_TWTR_165, MICRON_TCKE_165, \
  184. MICRON_TXP_165, MICRON_XSR_165)
  185. #define MICRON_RASWIDTH_165 13
  186. #define MICRON_V_MCFG_165(size) MCFG((size), MICRON_RASWIDTH_165)
  187. #define MICRON_BL_165 0x2
  188. #define MICRON_SIL_165 0x0
  189. #define MICRON_CASL_165 0x3
  190. #define MICRON_WBST_165 0x0
  191. #define MICRON_V_MR_165 ((MICRON_WBST_165 << 9) | \
  192. (MICRON_CASL_165 << 4) | (MICRON_SIL_165 << 3) | \
  193. (MICRON_BL_165))
  194. /* Micron part (200MHz optimized) 5 ns */
  195. #define MICRON_TDAL_200 6
  196. #define MICRON_TDPL_200 3
  197. #define MICRON_TRRD_200 2
  198. #define MICRON_TRCD_200 3
  199. #define MICRON_TRP_200 3
  200. #define MICRON_TRAS_200 8
  201. #define MICRON_TRC_200 11
  202. #define MICRON_TRFC_200 15
  203. #define MICRON_V_ACTIMA_200 \
  204. ACTIM_CTRLA(MICRON_TRFC_200, MICRON_TRC_200, \
  205. MICRON_TRAS_200, MICRON_TRP_200, \
  206. MICRON_TRCD_200, MICRON_TRRD_200, \
  207. MICRON_TDPL_200, MICRON_TDAL_200)
  208. #define MICRON_TWTR_200 2
  209. #define MICRON_TCKE_200 4
  210. #define MICRON_TXP_200 2
  211. #define MICRON_XSR_200 23
  212. #define MICRON_V_ACTIMB_200 \
  213. ACTIM_CTRLB(MICRON_TWTR_200, MICRON_TCKE_200, \
  214. MICRON_TXP_200, MICRON_XSR_200)
  215. #define MICRON_RASWIDTH_200 14
  216. #define MICRON_V_MCFG_200(size) MCFG((size), MICRON_RASWIDTH_200)
  217. /* NUMONYX part of IGEP v2 (165MHz optimized) 6.06ns */
  218. #define NUMONYX_TDAL_165 6 /* Twr/Tck + Trp/tck */
  219. /* 15/6 + 18/6 = 5.5 -> 6 */
  220. #define NUMONYX_TDPL_165 3 /* 15/6 = 2.5 -> 3 (Twr) */
  221. #define NUMONYX_TRRD_165 2 /* 12/6 = 2 */
  222. #define NUMONYX_TRCD_165 4 /* 22.5/6 = 3.75 -> 4 */
  223. #define NUMONYX_TRP_165 3 /* 18/6 = 3 */
  224. #define NUMONYX_TRAS_165 7 /* 42/6 = 7 */
  225. #define NUMONYX_TRC_165 10 /* 60/6 = 10 */
  226. #define NUMONYX_TRFC_165 24 /* 140/6 = 23.3 -> 24 */
  227. #define NUMONYX_V_ACTIMA_165 \
  228. ACTIM_CTRLA(NUMONYX_TRFC_165, NUMONYX_TRC_165, \
  229. NUMONYX_TRAS_165, NUMONYX_TRP_165, \
  230. NUMONYX_TRCD_165, NUMONYX_TRRD_165, \
  231. NUMONYX_TDPL_165, NUMONYX_TDAL_165)
  232. #define NUMONYX_TWTR_165 2
  233. #define NUMONYX_TCKE_165 2
  234. #define NUMONYX_TXP_165 3 /* 200/6 = 33.3 -> 34 */
  235. #define NUMONYX_XSR_165 34 /* 1.0 + 1.1 = 2.1 -> 3 */
  236. #define NUMONYX_V_ACTIMB_165 \
  237. ACTIM_CTRLB(NUMONYX_TWTR_165, NUMONYX_TCKE_165, \
  238. NUMONYX_TXP_165, NUMONYX_XSR_165)
  239. #define NUMONYX_RASWIDTH_165 15
  240. #define NUMONYX_V_MCFG_165(size) MCFG((size), NUMONYX_RASWIDTH_165)
  241. /* NUMONYX part of IGEP v2 (200MHz optimized) 5 ns */
  242. #define NUMONYX_TDAL_200 6 /* Twr/Tck + Trp/tck */
  243. /* 15/5 + 15/5 = 3 + 3 -> 6 */
  244. #define NUMONYX_TDPL_200 3 /* 15/5 = 3 -> 3 (Twr) */
  245. #define NUMONYX_TRRD_200 2 /* 10/5 = 2 */
  246. #define NUMONYX_TRCD_200 4 /* 16.2/5 = 3.24 -> 4 */
  247. #define NUMONYX_TRP_200 3 /* 15/5 = 3 */
  248. #define NUMONYX_TRAS_200 8 /* 40/5 = 8 */
  249. #define NUMONYX_TRC_200 11 /* 55/5 = 11 */
  250. #define NUMONYX_TRFC_200 28 /* 140/5 = 28 */
  251. #define NUMONYX_V_ACTIMA_200 \
  252. ACTIM_CTRLA(NUMONYX_TRFC_200, NUMONYX_TRC_200, \
  253. NUMONYX_TRAS_200, NUMONYX_TRP_200, \
  254. NUMONYX_TRCD_200, NUMONYX_TRRD_200, \
  255. NUMONYX_TDPL_200, NUMONYX_TDAL_200)
  256. #define NUMONYX_TWTR_200 2
  257. #define NUMONYX_TCKE_200 2
  258. #define NUMONYX_TXP_200 3
  259. #define NUMONYX_XSR_200 40
  260. #define NUMONYX_V_ACTIMB_200 \
  261. ACTIM_CTRLB(NUMONYX_TWTR_200, NUMONYX_TCKE_200, \
  262. NUMONYX_TXP_200, NUMONYX_XSR_200)
  263. #define NUMONYX_RASWIDTH_200 15
  264. #define NUMONYX_V_MCFG_200(size) MCFG((size), NUMONYX_RASWIDTH_200)
  265. /*
  266. * GPMC settings -
  267. * Definitions is as per the following format
  268. * #define <PART>_GPMC_CONFIG<x> <value>
  269. * Where:
  270. * PART is the part name e.g. STNOR - Intel Strata Flash
  271. * x is GPMC config registers from 1 to 6 (there will be 6 macros)
  272. * Value is corresponding value
  273. *
  274. * For every valid PRCM configuration there should be only one definition of
  275. * the same. if values are independent of the board, this definition will be
  276. * present in this file if values are dependent on the board, then this should
  277. * go into corresponding mem-boardName.h file
  278. *
  279. * Currently valid part Names are (PART):
  280. * STNOR - Intel Strata Flash
  281. * SMNAND - Samsung NAND
  282. * MPDB - H4 MPDB board
  283. * SBNOR - Sibley NOR
  284. * MNAND - Micron Large page x16 NAND
  285. * ONNAND - Samsung One NAND
  286. *
  287. * include/configs/file.h contains the defn - for all CS we are interested
  288. * #define OMAP34XX_GPMC_CSx PART
  289. * #define OMAP34XX_GPMC_CSx_SIZE Size
  290. * #define OMAP34XX_GPMC_CSx_MAP Map
  291. * Where:
  292. * x - CS number
  293. * PART - Part Name as defined above
  294. * SIZE - how big is the mapping to be
  295. * GPMC_SIZE_128M - 0x8
  296. * GPMC_SIZE_64M - 0xC
  297. * GPMC_SIZE_32M - 0xE
  298. * GPMC_SIZE_16M - 0xF
  299. * MAP - Map this CS to which address(GPMC address space)- Absolute address
  300. * >>24 before being used.
  301. */
  302. #define GPMC_SIZE_128M 0x8
  303. #define GPMC_SIZE_64M 0xC
  304. #define GPMC_SIZE_32M 0xE
  305. #define GPMC_SIZE_16M 0xF
  306. #define GPMC_BASEADDR_MASK 0x3F
  307. #define GPMC_CS_ENABLE 0x1
  308. #define SMNAND_GPMC_CONFIG1 0x00000800
  309. #define SMNAND_GPMC_CONFIG2 0x00141400
  310. #define SMNAND_GPMC_CONFIG3 0x00141400
  311. #define SMNAND_GPMC_CONFIG4 0x0F010F01
  312. #define SMNAND_GPMC_CONFIG5 0x010C1414
  313. #define SMNAND_GPMC_CONFIG6 0x1F0F0A80
  314. #define SMNAND_GPMC_CONFIG7 0x00000C44
  315. #define M_NAND_GPMC_CONFIG1 0x00001800
  316. #define M_NAND_GPMC_CONFIG2 0x00141400
  317. #define M_NAND_GPMC_CONFIG3 0x00141400
  318. #define M_NAND_GPMC_CONFIG4 0x0F010F01
  319. #define M_NAND_GPMC_CONFIG5 0x010C1414
  320. #define M_NAND_GPMC_CONFIG6 0x1f0f0A80
  321. #define M_NAND_GPMC_CONFIG7 0x00000C44
  322. #define STNOR_GPMC_CONFIG1 0x3
  323. #define STNOR_GPMC_CONFIG2 0x00151501
  324. #define STNOR_GPMC_CONFIG3 0x00060602
  325. #define STNOR_GPMC_CONFIG4 0x11091109
  326. #define STNOR_GPMC_CONFIG5 0x01141F1F
  327. #define STNOR_GPMC_CONFIG6 0x000004c4
  328. #define SIBNOR_GPMC_CONFIG1 0x1200
  329. #define SIBNOR_GPMC_CONFIG2 0x001f1f00
  330. #define SIBNOR_GPMC_CONFIG3 0x00080802
  331. #define SIBNOR_GPMC_CONFIG4 0x1C091C09
  332. #define SIBNOR_GPMC_CONFIG5 0x01131F1F
  333. #define SIBNOR_GPMC_CONFIG6 0x1F0F03C2
  334. #define SDPV2_MPDB_GPMC_CONFIG1 0x00611200
  335. #define SDPV2_MPDB_GPMC_CONFIG2 0x001F1F01
  336. #define SDPV2_MPDB_GPMC_CONFIG3 0x00080803
  337. #define SDPV2_MPDB_GPMC_CONFIG4 0x1D091D09
  338. #define SDPV2_MPDB_GPMC_CONFIG5 0x041D1F1F
  339. #define SDPV2_MPDB_GPMC_CONFIG6 0x1D0904C4
  340. #define MPDB_GPMC_CONFIG1 0x00011000
  341. #define MPDB_GPMC_CONFIG2 0x001f1f01
  342. #define MPDB_GPMC_CONFIG3 0x00080803
  343. #define MPDB_GPMC_CONFIG4 0x1c0b1c0a
  344. #define MPDB_GPMC_CONFIG5 0x041f1F1F
  345. #define MPDB_GPMC_CONFIG6 0x1F0F04C4
  346. #define P2_GPMC_CONFIG1 0x0
  347. #define P2_GPMC_CONFIG2 0x0
  348. #define P2_GPMC_CONFIG3 0x0
  349. #define P2_GPMC_CONFIG4 0x0
  350. #define P2_GPMC_CONFIG5 0x0
  351. #define P2_GPMC_CONFIG6 0x0
  352. #define ONENAND_GPMC_CONFIG1 0x00001200
  353. #define ONENAND_GPMC_CONFIG2 0x000F0F01
  354. #define ONENAND_GPMC_CONFIG3 0x00030301
  355. #define ONENAND_GPMC_CONFIG4 0x0F040F04
  356. #define ONENAND_GPMC_CONFIG5 0x010F1010
  357. #define ONENAND_GPMC_CONFIG6 0x1F060000
  358. #define NET_GPMC_CONFIG1 0x00001000
  359. #define NET_GPMC_CONFIG2 0x001e1e01
  360. #define NET_GPMC_CONFIG3 0x00080300
  361. #define NET_GPMC_CONFIG4 0x1c091c09
  362. #define NET_GPMC_CONFIG5 0x04181f1f
  363. #define NET_GPMC_CONFIG6 0x00000FCF
  364. #define NET_GPMC_CONFIG7 0x00000f6c
  365. /* max number of GPMC Chip Selects */
  366. #define GPMC_MAX_CS 8
  367. /* max number of GPMC regs */
  368. #define GPMC_MAX_REG 7
  369. #define PISMO1_NOR 1
  370. #define PISMO1_NAND 2
  371. #define PISMO2_CS0 3
  372. #define PISMO2_CS1 4
  373. #define PISMO1_ONENAND 5
  374. #define DBG_MPDB 6
  375. #define PISMO2_NAND_CS0 7
  376. #define PISMO2_NAND_CS1 8
  377. /* make it readable for the gpmc_init */
  378. #define PISMO1_NOR_BASE FLASH_BASE
  379. #define PISMO1_NAND_BASE NAND_BASE
  380. #define PISMO2_CS0_BASE PISMO2_MAP1
  381. #define PISMO1_ONEN_BASE ONENAND_MAP
  382. #define DBG_MPDB_BASE DEBUG_BASE
  383. #ifndef __ASSEMBLY__
  384. /* Function prototypes */
  385. void mem_init(void);
  386. u32 is_mem_sdr(void);
  387. u32 mem_ok(u32 cs);
  388. u32 get_sdr_cs_size(u32);
  389. u32 get_sdr_cs_offset(u32);
  390. #endif /* __ASSEMBLY__ */
  391. #endif /* endif _MEM_H_ */