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u-boot
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arch
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arm
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include
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asm
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arch-omap3
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dma.h

dma.h 2.4 KB
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  1. #ifndef __SDMA_H
    2. 

  2. #define __SDMA_H
    3. 

  3. 

  4. /* Copyright (C) 2011
    5. 

  5.  * Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de>
    6. 

  6.  *
    7. 

  7.  * SPDX-License-Identifier:	GPL-2.0+
    8. 

  8.  */
    9. 

  9. 

  10. /* Functions */
    11. 

  11. void omap3_dma_init(void);
    12. 

  12. int omap3_dma_conf_transfer(uint32_t chan, uint32_t *src, uint32_t *dst,
    13. 

  13. 		uint32_t sze);
    14. 

  14. int omap3_dma_start_transfer(uint32_t chan);
    15. 

  15. int omap3_dma_wait_for_transfer(uint32_t chan);
    16. 

  16. int omap3_dma_conf_chan(uint32_t chan, struct dma4_chan *config);
    17. 

  17. int omap3_dma_get_conf_chan(uint32_t chan, struct dma4_chan *config);
    18. 

  18. 

  19. /* Register settings */
    20. 

  20. #define CSDP_DATA_TYPE_8BIT             0x0
    21. 

  21. #define CSDP_DATA_TYPE_16BIT            0x1
    22. 

  22. #define CSDP_DATA_TYPE_32BIT            0x2
    23. 

  23. #define CSDP_SRC_BURST_SINGLE           (0x0 << 7)
    24. 

  24. #define CSDP_SRC_BURST_EN_16BYTES       (0x1 << 7)
    25. 

  25. #define CSDP_SRC_BURST_EN_32BYTES       (0x2 << 7)
    26. 

  26. #define CSDP_SRC_BURST_EN_64BYTES       (0x3 << 7)
    27. 

  27. #define CSDP_DST_BURST_SINGLE           (0x0 << 14)
    28. 

  28. #define CSDP_DST_BURST_EN_16BYTES       (0x1 << 14)
    29. 

  29. #define CSDP_DST_BURST_EN_32BYTES       (0x2 << 14)
    30. 

  30. #define CSDP_DST_BURST_EN_64BYTES       (0x3 << 14)
    31. 

  31. #define CSDP_DST_ENDIAN_LOCK_ADAPT      (0x0 << 18)
    32. 

  32. #define CSDP_DST_ENDIAN_LOCK_LOCK       (0x1 << 18)
    33. 

  33. #define CSDP_DST_ENDIAN_LITTLE          (0x0 << 19)
    34. 

  34. #define CSDP_DST_ENDIAN_BIG             (0x1 << 19)
    35. 

  35. #define CSDP_SRC_ENDIAN_LOCK_ADAPT      (0x0 << 20)
    36. 

  36. #define CSDP_SRC_ENDIAN_LOCK_LOCK       (0x1 << 20)
    37. 

  37. #define CSDP_SRC_ENDIAN_LITTLE          (0x0 << 21)
    38. 

  38. #define CSDP_SRC_ENDIAN_BIG             (0x1 << 21)
    39. 

  39. 

  40. #define CCR_READ_PRIORITY_LOW           (0x0 << 6)
    41. 

  41. #define CCR_READ_PRIORITY_HIGH          (0x1 << 6)
    42. 

  42. #define CCR_ENABLE_DISABLED             (0x0 << 7)
    43. 

  43. #define CCR_ENABLE_ENABLE               (0x1 << 7)
    44. 

  44. #define CCR_SRC_AMODE_CONSTANT          (0x0 << 12)
    45. 

  45. #define CCR_SRC_AMODE_POST_INC          (0x1 << 12)
    46. 

  46. #define CCR_SRC_AMODE_SINGLE_IDX        (0x2 << 12)
    47. 

  47. #define CCR_SRC_AMODE_DOUBLE_IDX        (0x3 << 12)
    48. 

  48. #define CCR_DST_AMODE_CONSTANT          (0x0 << 14)
    49. 

  49. #define CCR_DST_AMODE_POST_INC          (0x1 << 14)
    50. 

  50. #define CCR_DST_AMODE_SINGLE_IDX        (0x2 << 14)
    51. 

  51. #define CCR_DST_AMODE_SOUBLE_IDX        (0x3 << 14)
    52. 

  52. 

  53. #define CCR_RD_ACTIVE_MASK              (1 << 9)
    54. 

  54. #define CCR_WR_ACTIVE_MASK              (1 << 10)
    55. 

  55. 

  56. #define CSR_TRANS_ERR			(1 << 8)
    57. 

  57. #define CSR_SUPERVISOR_ERR		(1 << 10)
    58. 

  58. #define CSR_MISALIGNED_ADRS_ERR		(1 << 11)
    59. 

  59. 

  60. /* others */
    61. 

  61. #define CHAN_NR_MIN			0
    62. 

  62. #define CHAN_NR_MAX			31
    63. 

  63. 

  64. #endif /* __SDMA_H */
    65.