clocks_omap3.h 7.9 KB

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  1. /*
  2. * (C) Copyright 2006-2008
  3. * Texas Instruments, <www.ti.com>
  4. * Richard Woodruff <r-woodruff2@ti.com>
  5. *
  6. * SPDX-License-Identifier: GPL-2.0+
  7. */
  8. #ifndef _CLOCKS_OMAP3_H_
  9. #define _CLOCKS_OMAP3_H_
  10. #define PLL_STOP 1 /* PER & IVA */
  11. #define PLL_LOW_POWER_BYPASS 5 /* MPU, IVA & CORE */
  12. #define PLL_FAST_RELOCK_BYPASS 6 /* CORE */
  13. #define PLL_LOCK 7 /* MPU, IVA, CORE & PER */
  14. /*
  15. * The following configurations are OPP and SysClk value independant
  16. * and hence are defined here. All the other DPLL related values are
  17. * tabulated in lowlevel_init.S.
  18. */
  19. /* CORE DPLL */
  20. #define CORE_M3X2 2 /* 332MHz : CM_CLKSEL1_EMU */
  21. #define CORE_SSI_DIV 3 /* 221MHz : CM_CLKSEL_CORE */
  22. #define CORE_FUSB_DIV 2 /* 41.5MHz: */
  23. #define CORE_L4_DIV 2 /* 83MHz : L4 */
  24. #define CORE_L3_DIV 2 /* 166MHz : L3 {DDR} */
  25. #define GFX_DIV 2 /* 83MHz : CM_CLKSEL_GFX */
  26. #define GFX_DIV_36X 5 /* 200MHz : CM_CLKSEL_GFX */
  27. #define WKUP_RSM 2 /* 41.5MHz: CM_CLKSEL_WKUP */
  28. /* PER DPLL */
  29. #define PER_M6X2 3 /* 288MHz: CM_CLKSEL1_EMU */
  30. #define PER_M5X2 4 /* 216MHz: CM_CLKSEL_CAM */
  31. #define PER_M4X2 2 /* 432MHz: CM_CLKSEL_DSS-dss1 */
  32. #define PER_M3X2 16 /* 54MHz : CM_CLKSEL_DSS-tv */
  33. #define CLSEL1_EMU_VAL ((CORE_M3X2 << 16) | (PER_M6X2 << 24) | (0x0A50))
  34. /* MPU DPLL */
  35. #define MPU_M_12_ES1 0x0FE
  36. #define MPU_N_12_ES1 0x07
  37. #define MPU_FSEL_12_ES1 0x05
  38. #define MPU_M2_12_ES1 0x01
  39. #define MPU_M_12_ES2 0x0FA
  40. #define MPU_N_12_ES2 0x05
  41. #define MPU_FSEL_12_ES2 0x07
  42. #define MPU_M2_ES2 0x01
  43. #define MPU_M_12 0x085
  44. #define MPU_N_12 0x05
  45. #define MPU_FSEL_12 0x07
  46. #define MPU_M2_12 0x01
  47. #define MPU_M_13_ES1 0x17D
  48. #define MPU_N_13_ES1 0x0C
  49. #define MPU_FSEL_13_ES1 0x03
  50. #define MPU_M2_13_ES1 0x01
  51. #define MPU_M_13_ES2 0x258
  52. #define MPU_N_13_ES2 0x0C
  53. #define MPU_FSEL_13_ES2 0x03
  54. #define MPU_M2_13_ES2 0x01
  55. #define MPU_M_13 0x10A
  56. #define MPU_N_13 0x0C
  57. #define MPU_FSEL_13 0x03
  58. #define MPU_M2_13 0x01
  59. #define MPU_M_19P2_ES1 0x179
  60. #define MPU_N_19P2_ES1 0x12
  61. #define MPU_FSEL_19P2_ES1 0x04
  62. #define MPU_M2_19P2_ES1 0x01
  63. #define MPU_M_19P2_ES2 0x271
  64. #define MPU_N_19P2_ES2 0x17
  65. #define MPU_FSEL_19P2_ES2 0x03
  66. #define MPU_M2_19P2_ES2 0x01
  67. #define MPU_M_19P2 0x14C
  68. #define MPU_N_19P2 0x17
  69. #define MPU_FSEL_19P2 0x03
  70. #define MPU_M2_19P2 0x01
  71. #define MPU_M_26_ES1 0x17D
  72. #define MPU_N_26_ES1 0x19
  73. #define MPU_FSEL_26_ES1 0x03
  74. #define MPU_M2_26_ES1 0x01
  75. #define MPU_M_26_ES2 0x0FA
  76. #define MPU_N_26_ES2 0x0C
  77. #define MPU_FSEL_26_ES2 0x07
  78. #define MPU_M2_26_ES2 0x01
  79. #define MPU_M_26 0x085
  80. #define MPU_N_26 0x0C
  81. #define MPU_FSEL_26 0x07
  82. #define MPU_M2_26 0x01
  83. #define MPU_M_38P4_ES1 0x1FA
  84. #define MPU_N_38P4_ES1 0x32
  85. #define MPU_FSEL_38P4_ES1 0x03
  86. #define MPU_M2_38P4_ES1 0x01
  87. #define MPU_M_38P4_ES2 0x271
  88. #define MPU_N_38P4_ES2 0x2F
  89. #define MPU_FSEL_38P4_ES2 0x03
  90. #define MPU_M2_38P4_ES2 0x01
  91. #define MPU_M_38P4 0x14C
  92. #define MPU_N_38P4 0x2F
  93. #define MPU_FSEL_38P4 0x03
  94. #define MPU_M2_38P4 0x01
  95. /* IVA DPLL */
  96. #define IVA_M_12_ES1 0x07D
  97. #define IVA_N_12_ES1 0x05
  98. #define IVA_FSEL_12_ES1 0x07
  99. #define IVA_M2_12_ES1 0x01
  100. #define IVA_M_12_ES2 0x0B4
  101. #define IVA_N_12_ES2 0x05
  102. #define IVA_FSEL_12_ES2 0x07
  103. #define IVA_M2_12_ES2 0x01
  104. #define IVA_M_12 0x085
  105. #define IVA_N_12 0x05
  106. #define IVA_FSEL_12 0x07
  107. #define IVA_M2_12 0x01
  108. #define IVA_M_13_ES1 0x0FA
  109. #define IVA_N_13_ES1 0x0C
  110. #define IVA_FSEL_13_ES1 0x03
  111. #define IVA_M2_13_ES1 0x01
  112. #define IVA_M_13_ES2 0x168
  113. #define IVA_N_13_ES2 0x0C
  114. #define IVA_FSEL_13_ES2 0x03
  115. #define IVA_M2_13_ES2 0x01
  116. #define IVA_M_13 0x10A
  117. #define IVA_N_13 0x0C
  118. #define IVA_FSEL_13 0x03
  119. #define IVA_M2_13 0x01
  120. #define IVA_M_19P2_ES1 0x082
  121. #define IVA_N_19P2_ES1 0x09
  122. #define IVA_FSEL_19P2_ES1 0x07
  123. #define IVA_M2_19P2_ES1 0x01
  124. #define IVA_M_19P2_ES2 0x0E1
  125. #define IVA_N_19P2_ES2 0x0B
  126. #define IVA_FSEL_19P2_ES2 0x06
  127. #define IVA_M2_19P2_ES2 0x01
  128. #define IVA_M_19P2 0x14C
  129. #define IVA_N_19P2 0x17
  130. #define IVA_FSEL_19P2 0x03
  131. #define IVA_M2_19P2 0x01
  132. #define IVA_M_26_ES1 0x07D
  133. #define IVA_N_26_ES1 0x0C
  134. #define IVA_FSEL_26_ES1 0x07
  135. #define IVA_M2_26_ES1 0x01
  136. #define IVA_M_26_ES2 0x0B4
  137. #define IVA_N_26_ES2 0x0C
  138. #define IVA_FSEL_26_ES2 0x07
  139. #define IVA_M2_26_ES2 0x01
  140. #define IVA_M_26 0x085
  141. #define IVA_N_26 0x0C
  142. #define IVA_FSEL_26 0x07
  143. #define IVA_M2_26 0x01
  144. #define IVA_M_38P4_ES1 0x13F
  145. #define IVA_N_38P4_ES1 0x30
  146. #define IVA_FSEL_38P4_ES1 0x03
  147. #define IVA_M2_38P4_ES1 0x01
  148. #define IVA_M_38P4_ES2 0x0E1
  149. #define IVA_N_38P4_ES2 0x17
  150. #define IVA_FSEL_38P4_ES2 0x06
  151. #define IVA_M2_38P4_ES2 0x01
  152. #define IVA_M_38P4 0x14C
  153. #define IVA_N_38P4 0x2F
  154. #define IVA_FSEL_38P4 0x03
  155. #define IVA_M2_38P4 0x01
  156. /* CORE DPLL */
  157. #define CORE_M_12 0xA6
  158. #define CORE_N_12 0x05
  159. #define CORE_FSEL_12 0x07
  160. #define CORE_M2_12 0x01 /* M3 of 2 */
  161. #define CORE_M_12_ES1 0x19F
  162. #define CORE_N_12_ES1 0x0E
  163. #define CORE_FSL_12_ES1 0x03
  164. #define CORE_M2_12_ES1 0x1 /* M3 of 2 */
  165. #define CORE_M_13 0x14C
  166. #define CORE_N_13 0x0C
  167. #define CORE_FSEL_13 0x03
  168. #define CORE_M2_13 0x01 /* M3 of 2 */
  169. #define CORE_M_13_ES1 0x1B2
  170. #define CORE_N_13_ES1 0x10
  171. #define CORE_FSL_13_ES1 0x03
  172. #define CORE_M2_13_ES1 0x01 /* M3 of 2 */
  173. #define CORE_M_19P2 0x19F
  174. #define CORE_N_19P2 0x17
  175. #define CORE_FSEL_19P2 0x03
  176. #define CORE_M2_19P2 0x01 /* M3 of 2 */
  177. #define CORE_M_19P2_ES1 0x19F
  178. #define CORE_N_19P2_ES1 0x17
  179. #define CORE_FSL_19P2_ES1 0x03
  180. #define CORE_M2_19P2_ES1 0x01 /* M3 of 2 */
  181. #define CORE_M_26 0xA6
  182. #define CORE_N_26 0x0C
  183. #define CORE_FSEL_26 0x07
  184. #define CORE_M2_26 0x01 /* M3 of 2 */
  185. #define CORE_M_26_ES1 0x1B2
  186. #define CORE_N_26_ES1 0x21
  187. #define CORE_FSL_26_ES1 0x03
  188. #define CORE_M2_26_ES1 0x01 /* M3 of 2 */
  189. #define CORE_M_38P4 0x19F
  190. #define CORE_N_38P4 0x2F
  191. #define CORE_FSEL_38P4 0x03
  192. #define CORE_M2_38P4 0x01 /* M3 of 2 */
  193. #define CORE_M_38P4_ES1 0x19F
  194. #define CORE_N_38P4_ES1 0x2F
  195. #define CORE_FSL_38P4_ES1 0x03
  196. #define CORE_M2_38P4_ES1 0x01 /* M3 of 2 */
  197. /* PER DPLL */
  198. #define PER_M_12 0xD8
  199. #define PER_N_12 0x05
  200. #define PER_FSEL_12 0x07
  201. #define PER_M2_12 0x09
  202. #define PER_M_13 0x1B0
  203. #define PER_N_13 0x0C
  204. #define PER_FSEL_13 0x03
  205. #define PER_M2_13 0x09
  206. #define PER_M_19P2 0xE1
  207. #define PER_N_19P2 0x09
  208. #define PER_FSEL_19P2 0x07
  209. #define PER_M2_19P2 0x09
  210. #define PER_M_26 0xD8
  211. #define PER_N_26 0x0C
  212. #define PER_FSEL_26 0x07
  213. #define PER_M2_26 0x09
  214. #define PER_M_38P4 0xE1
  215. #define PER_N_38P4 0x13
  216. #define PER_FSEL_38P4 0x07
  217. #define PER_M2_38P4 0x09
  218. /* PER2 DPLL */
  219. #define PER2_M_12 0x78
  220. #define PER2_N_12 0x0B
  221. #define PER2_FSEL_12 0x03
  222. #define PER2_M2_12 0x01
  223. #define PER2_M_13 0x78
  224. #define PER2_N_13 0x0C
  225. #define PER2_FSEL_13 0x03
  226. #define PER2_M2_13 0x01
  227. #define PER2_M_19P2 0x2EE
  228. #define PER2_N_19P2 0x0B
  229. #define PER2_FSEL_19P2 0x06
  230. #define PER2_M2_19P2 0x0A
  231. #define PER2_M_26 0x78
  232. #define PER2_N_26 0x0C
  233. #define PER2_FSEL_26 0x03
  234. #define PER2_M2_26 0x01
  235. #define PER2_M_38P4 0x2EE
  236. #define PER2_N_38P4 0x0B
  237. #define PER2_FSEL_38P4 0x06
  238. #define PER2_M2_38P4 0x0A
  239. /* 36XX PER DPLL */
  240. #define PER_36XX_M_12 0x1B0
  241. #define PER_36XX_N_12 0x05
  242. #define PER_36XX_FSEL_12 0x07
  243. #define PER_36XX_M2_12 0x09
  244. #define PER_36XX_M_13 0x360
  245. #define PER_36XX_N_13 0x0C
  246. #define PER_36XX_FSEL_13 0x03
  247. #define PER_36XX_M2_13 0x09
  248. #define PER_36XX_M_19P2 0x1C2
  249. #define PER_36XX_N_19P2 0x09
  250. #define PER_36XX_FSEL_19P2 0x07
  251. #define PER_36XX_M2_19P2 0x09
  252. #define PER_36XX_M_26 0x1B0
  253. #define PER_36XX_N_26 0x0C
  254. #define PER_36XX_FSEL_26 0x07
  255. #define PER_36XX_M2_26 0x09
  256. #define PER_36XX_M_38P4 0x1C2
  257. #define PER_36XX_N_38P4 0x13
  258. #define PER_36XX_FSEL_38P4 0x07
  259. #define PER_36XX_M2_38P4 0x09
  260. /* 36XX PER2 DPLL */
  261. #define PER2_36XX_M_12 0x50
  262. #define PER2_36XX_N_12 0x00
  263. #define PER2_36XX_M2_12 0x08
  264. #define PER2_36XX_M_13 0x1BB
  265. #define PER2_36XX_N_13 0x05
  266. #define PER2_36XX_M2_13 0x08
  267. #define PER2_36XX_M_19P2 0x32
  268. #define PER2_36XX_N_19P2 0x00
  269. #define PER2_36XX_M2_19P2 0x08
  270. #define PER2_36XX_M_26 0x1BB
  271. #define PER2_36XX_N_26 0x0B
  272. #define PER2_36XX_M2_26 0x08
  273. #define PER2_36XX_M_38P4 0x19
  274. #define PER2_36XX_N_38P4 0x00
  275. #define PER2_36XX_M2_38P4 0x08
  276. #endif /* endif _CLOCKS_OMAP3_H_ */