emif_defs.h 1.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172
  1. /*
  2. * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #ifndef _EMIF_DEFS_H_
  7. #define _EMIF_DEFS_H_
  8. #include <asm/arch/hardware.h>
  9. struct davinci_emif_regs {
  10. u_int32_t ercsr;
  11. u_int32_t awccr;
  12. u_int32_t sdbcr;
  13. u_int32_t sdrcr;
  14. u_int32_t ab1cr;
  15. u_int32_t ab2cr;
  16. u_int32_t ab3cr;
  17. u_int32_t ab4cr;
  18. u_int32_t sdtimr;
  19. u_int32_t ddrsr;
  20. u_int32_t ddrphycr;
  21. u_int32_t ddrphysr;
  22. u_int32_t totar;
  23. u_int32_t totactr;
  24. u_int32_t ddrphyid_rev;
  25. u_int32_t sdsretr;
  26. u_int32_t eirr;
  27. u_int32_t eimr;
  28. u_int32_t eimsr;
  29. u_int32_t eimcr;
  30. u_int32_t ioctrlr;
  31. u_int32_t iostatr;
  32. u_int8_t rsvd0[8];
  33. u_int32_t nandfcr;
  34. u_int32_t nandfsr;
  35. u_int8_t rsvd1[8];
  36. u_int32_t nandfecc[4];
  37. u_int8_t rsvd2[60];
  38. u_int32_t nand4biteccload;
  39. u_int32_t nand4bitecc[4];
  40. u_int32_t nanderradd1;
  41. u_int32_t nanderradd2;
  42. u_int32_t nanderrval1;
  43. u_int32_t nanderrval2;
  44. };
  45. #define davinci_emif_regs \
  46. ((struct davinci_emif_regs *)DAVINCI_ASYNC_EMIF_CNTRL_BASE)
  47. #define DAVINCI_NANDFCR_NAND_ENABLE(n) (1 << (n-2))
  48. #define DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK (3 << 4)
  49. #define DAVINCI_NANDFCR_4BIT_ECC_SEL(n) ((n-2) << 4)
  50. #define DAVINCI_NANDFCR_1BIT_ECC_START(n) (1 << (8 + (n-2)))
  51. #define DAVINCI_NANDFCR_4BIT_ECC_START (1 << 12)
  52. #define DAVINCI_NANDFCR_4BIT_CALC_START (1 << 13)
  53. #define DAVINCI_NANDFCR_CS2NAND (1 << 0)
  54. /* Chip Select setup */
  55. #define DAVINCI_ABCR_STROBE_SELECT (1 << 31)
  56. #define DAVINCI_ABCR_EXT_WAIT (1 << 30)
  57. #define DAVINCI_ABCR_WSETUP(n) (n << 26)
  58. #define DAVINCI_ABCR_WSTROBE(n) (n << 20)
  59. #define DAVINCI_ABCR_WHOLD(n) (n << 17)
  60. #define DAVINCI_ABCR_RSETUP(n) (n << 13)
  61. #define DAVINCI_ABCR_RSTROBE(n) (n << 7)
  62. #define DAVINCI_ABCR_RHOLD(n) (n << 4)
  63. #define DAVINCI_ABCR_TA(n) (n << 2)
  64. #define DAVINCI_ABCR_ASIZE_16BIT 1
  65. #define DAVINCI_ABCR_ASIZE_8BIT 0
  66. #endif