denali_spl.c 4.6 KB

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  1. /*
  2. * Copyright (C) 2014 Panasonic Corporation
  3. * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. #include <common.h>
  8. #include <asm/io.h>
  9. #include <asm/unaligned.h>
  10. #include <linux/mtd/nand.h>
  11. #include "denali.h"
  12. #define SPARE_ACCESS 0x41
  13. #define MAIN_ACCESS 0x42
  14. #define PIPELINE_ACCESS 0x2000
  15. #define BANK(x) ((x) << 24)
  16. static void __iomem *denali_flash_mem =
  17. (void __iomem *)CONFIG_SYS_NAND_DATA_BASE;
  18. static void __iomem *denali_flash_reg =
  19. (void __iomem *)CONFIG_SYS_NAND_REGS_BASE;
  20. static const int flash_bank;
  21. static int page_size, oob_size, pages_per_block;
  22. static void index_addr(uint32_t address, uint32_t data)
  23. {
  24. writel(address, denali_flash_mem + INDEX_CTRL_REG);
  25. writel(data, denali_flash_mem + INDEX_DATA_REG);
  26. }
  27. static int wait_for_irq(uint32_t irq_mask)
  28. {
  29. unsigned long timeout = 1000000;
  30. uint32_t intr_status;
  31. do {
  32. intr_status = readl(denali_flash_reg + INTR_STATUS(flash_bank));
  33. if (intr_status & INTR_STATUS__ECC_UNCOR_ERR) {
  34. debug("Uncorrected ECC detected\n");
  35. return -EBADMSG;
  36. }
  37. if (intr_status & irq_mask)
  38. break;
  39. udelay(1);
  40. timeout--;
  41. } while (timeout);
  42. if (!timeout) {
  43. debug("Timeout with interrupt status %08x\n", intr_status);
  44. return -EIO;
  45. }
  46. return 0;
  47. }
  48. static void read_data_from_flash_mem(uint8_t *buf, int len)
  49. {
  50. int i;
  51. uint32_t *buf32;
  52. /* transfer the data from the flash */
  53. buf32 = (uint32_t *)buf;
  54. /*
  55. * Let's take care of unaligned access although it rarely happens.
  56. * Avoid put_unaligned() for the normal use cases since it leads to
  57. * a bit performance regression.
  58. */
  59. if ((unsigned long)buf32 % 4) {
  60. for (i = 0; i < len / 4; i++)
  61. put_unaligned(readl(denali_flash_mem + INDEX_DATA_REG),
  62. buf32++);
  63. } else {
  64. for (i = 0; i < len / 4; i++)
  65. *buf32++ = readl(denali_flash_mem + INDEX_DATA_REG);
  66. }
  67. if (len % 4) {
  68. u32 tmp;
  69. tmp = cpu_to_le32(readl(denali_flash_mem + INDEX_DATA_REG));
  70. buf = (uint8_t *)buf32;
  71. for (i = 0; i < len % 4; i++) {
  72. *buf++ = tmp;
  73. tmp >>= 8;
  74. }
  75. }
  76. }
  77. int denali_send_pipeline_cmd(int page, int ecc_en, int access_type)
  78. {
  79. uint32_t addr, cmd;
  80. static uint32_t page_count = 1;
  81. writel(ecc_en, denali_flash_reg + ECC_ENABLE);
  82. /* clear all bits of intr_status. */
  83. writel(0xffff, denali_flash_reg + INTR_STATUS(flash_bank));
  84. addr = BANK(flash_bank) | page;
  85. /* setup the acccess type */
  86. cmd = MODE_10 | addr;
  87. index_addr(cmd, access_type);
  88. /* setup the pipeline command */
  89. index_addr(cmd, PIPELINE_ACCESS | page_count);
  90. cmd = MODE_01 | addr;
  91. writel(cmd, denali_flash_mem + INDEX_CTRL_REG);
  92. return wait_for_irq(INTR_STATUS__LOAD_COMP);
  93. }
  94. static int nand_read_oob(void *buf, int page)
  95. {
  96. int ret;
  97. ret = denali_send_pipeline_cmd(page, 0, SPARE_ACCESS);
  98. if (ret < 0)
  99. return ret;
  100. read_data_from_flash_mem(buf, oob_size);
  101. return 0;
  102. }
  103. static int nand_read_page(void *buf, int page)
  104. {
  105. int ret;
  106. ret = denali_send_pipeline_cmd(page, 1, MAIN_ACCESS);
  107. if (ret < 0)
  108. return ret;
  109. read_data_from_flash_mem(buf, page_size);
  110. return 0;
  111. }
  112. static int nand_block_isbad(void *buf, int block)
  113. {
  114. int ret;
  115. ret = nand_read_oob(buf, block * pages_per_block);
  116. if (ret < 0)
  117. return ret;
  118. return *((uint8_t *)buf + CONFIG_SYS_NAND_BAD_BLOCK_POS) != 0xff;
  119. }
  120. /* nand_init() - initialize data to make nand usable by SPL */
  121. void nand_init(void)
  122. {
  123. /* access to main area */
  124. writel(0, denali_flash_reg + TRANSFER_SPARE_REG);
  125. /*
  126. * These registers are expected to be already set by the hardware
  127. * or earlier boot code. So we read these values out.
  128. */
  129. page_size = readl(denali_flash_reg + DEVICE_MAIN_AREA_SIZE);
  130. oob_size = readl(denali_flash_reg + DEVICE_SPARE_AREA_SIZE);
  131. pages_per_block = readl(denali_flash_reg + PAGES_PER_BLOCK);
  132. }
  133. int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
  134. {
  135. int block, page, column, readlen;
  136. int ret;
  137. int force_bad_block_check = 1;
  138. page = offs / page_size;
  139. column = offs % page_size;
  140. block = page / pages_per_block;
  141. page = page % pages_per_block;
  142. while (size) {
  143. if (force_bad_block_check || page == 0) {
  144. ret = nand_block_isbad(dst, block);
  145. if (ret < 0)
  146. return ret;
  147. if (ret) {
  148. block++;
  149. continue;
  150. }
  151. }
  152. force_bad_block_check = 0;
  153. ret = nand_read_page(dst, block * pages_per_block + page);
  154. if (ret < 0)
  155. return ret;
  156. readlen = min(page_size - column, (int)size);
  157. if (unlikely(column)) {
  158. /* Partial page read */
  159. memmove(dst, dst + column, readlen);
  160. column = 0;
  161. }
  162. size -= readlen;
  163. dst += readlen;
  164. page++;
  165. if (page == pages_per_block) {
  166. block++;
  167. page = 0;
  168. }
  169. }
  170. return 0;
  171. }
  172. void nand_deselect(void) {}