altera_qspi.c 8.9 KB

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  1. /*
  2. * Copyright (C) 2015 Thomas Chou <thomas@wytron.com.tw>
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #include <common.h>
  7. #include <dm.h>
  8. #include <errno.h>
  9. #include <fdt_support.h>
  10. #include <flash.h>
  11. #include <mtd.h>
  12. #include <asm/io.h>
  13. DECLARE_GLOBAL_DATA_PTR;
  14. /* The STATUS register */
  15. #define QUADSPI_SR_BP0 BIT(2)
  16. #define QUADSPI_SR_BP1 BIT(3)
  17. #define QUADSPI_SR_BP2 BIT(4)
  18. #define QUADSPI_SR_BP2_0 GENMASK(4, 2)
  19. #define QUADSPI_SR_BP3 BIT(6)
  20. #define QUADSPI_SR_TB BIT(5)
  21. /*
  22. * The QUADSPI_MEM_OP register is used to do memory protect and erase operations
  23. */
  24. #define QUADSPI_MEM_OP_BULK_ERASE 0x00000001
  25. #define QUADSPI_MEM_OP_SECTOR_ERASE 0x00000002
  26. #define QUADSPI_MEM_OP_SECTOR_PROTECT 0x00000003
  27. /*
  28. * The QUADSPI_ISR register is used to determine whether an invalid write or
  29. * erase operation trigerred an interrupt
  30. */
  31. #define QUADSPI_ISR_ILLEGAL_ERASE BIT(0)
  32. #define QUADSPI_ISR_ILLEGAL_WRITE BIT(1)
  33. struct altera_qspi_regs {
  34. u32 rd_status;
  35. u32 rd_sid;
  36. u32 rd_rdid;
  37. u32 mem_op;
  38. u32 isr;
  39. u32 imr;
  40. u32 chip_select;
  41. };
  42. struct altera_qspi_platdata {
  43. struct altera_qspi_regs *regs;
  44. void *base;
  45. unsigned long size;
  46. };
  47. flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* FLASH chips info */
  48. static void altera_qspi_get_locked_range(struct mtd_info *mtd, loff_t *ofs,
  49. uint64_t *len);
  50. void flash_print_info(flash_info_t *info)
  51. {
  52. struct mtd_info *mtd = info->mtd;
  53. loff_t ofs;
  54. u64 len;
  55. printf("Altera QSPI flash Size: %ld MB in %d Sectors\n",
  56. info->size >> 20, info->sector_count);
  57. altera_qspi_get_locked_range(mtd, &ofs, &len);
  58. printf(" %08lX +%lX", info->start[0], info->size);
  59. if (len) {
  60. printf(", protected %08llX +%llX",
  61. info->start[0] + ofs, len);
  62. }
  63. putc('\n');
  64. }
  65. int flash_erase(flash_info_t *info, int s_first, int s_last)
  66. {
  67. struct mtd_info *mtd = info->mtd;
  68. struct erase_info instr;
  69. int ret;
  70. memset(&instr, 0, sizeof(instr));
  71. instr.addr = mtd->erasesize * s_first;
  72. instr.len = mtd->erasesize * (s_last + 1 - s_first);
  73. ret = mtd_erase(mtd, &instr);
  74. if (ret)
  75. return ERR_PROTECTED;
  76. return 0;
  77. }
  78. int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
  79. {
  80. struct mtd_info *mtd = info->mtd;
  81. struct udevice *dev = mtd->dev;
  82. struct altera_qspi_platdata *pdata = dev_get_platdata(dev);
  83. ulong base = (ulong)pdata->base;
  84. loff_t to = addr - base;
  85. size_t retlen;
  86. int ret;
  87. ret = mtd_write(mtd, to, cnt, &retlen, src);
  88. if (ret)
  89. return ERR_PROTECTED;
  90. return 0;
  91. }
  92. unsigned long flash_init(void)
  93. {
  94. struct udevice *dev;
  95. /* probe every MTD device */
  96. for (uclass_first_device(UCLASS_MTD, &dev);
  97. dev;
  98. uclass_next_device(&dev)) {
  99. }
  100. return flash_info[0].size;
  101. }
  102. static int altera_qspi_erase(struct mtd_info *mtd, struct erase_info *instr)
  103. {
  104. struct udevice *dev = mtd->dev;
  105. struct altera_qspi_platdata *pdata = dev_get_platdata(dev);
  106. struct altera_qspi_regs *regs = pdata->regs;
  107. size_t addr = instr->addr;
  108. size_t len = instr->len;
  109. size_t end = addr + len;
  110. u32 sect;
  111. u32 stat;
  112. instr->state = MTD_ERASING;
  113. addr &= ~(mtd->erasesize - 1); /* get lower aligned address */
  114. while (addr < end) {
  115. sect = addr / mtd->erasesize;
  116. sect <<= 8;
  117. sect |= QUADSPI_MEM_OP_SECTOR_ERASE;
  118. debug("erase %08x\n", sect);
  119. writel(sect, &regs->mem_op);
  120. stat = readl(&regs->isr);
  121. if (stat & QUADSPI_ISR_ILLEGAL_ERASE) {
  122. /* erase failed, sector might be protected */
  123. debug("erase %08x fail %x\n", sect, stat);
  124. writel(stat, &regs->isr); /* clear isr */
  125. instr->state = MTD_ERASE_FAILED;
  126. return -EIO;
  127. }
  128. addr += mtd->erasesize;
  129. }
  130. instr->state = MTD_ERASE_DONE;
  131. mtd_erase_callback(instr);
  132. return 0;
  133. }
  134. static int altera_qspi_read(struct mtd_info *mtd, loff_t from, size_t len,
  135. size_t *retlen, u_char *buf)
  136. {
  137. struct udevice *dev = mtd->dev;
  138. struct altera_qspi_platdata *pdata = dev_get_platdata(dev);
  139. memcpy_fromio(buf, pdata->base + from, len);
  140. *retlen = len;
  141. return 0;
  142. }
  143. static int altera_qspi_write(struct mtd_info *mtd, loff_t to, size_t len,
  144. size_t *retlen, const u_char *buf)
  145. {
  146. struct udevice *dev = mtd->dev;
  147. struct altera_qspi_platdata *pdata = dev_get_platdata(dev);
  148. struct altera_qspi_regs *regs = pdata->regs;
  149. u32 stat;
  150. memcpy_toio(pdata->base + to, buf, len);
  151. /* check whether write triggered a illegal write interrupt */
  152. stat = readl(&regs->isr);
  153. if (stat & QUADSPI_ISR_ILLEGAL_WRITE) {
  154. /* write failed, sector might be protected */
  155. debug("write fail %x\n", stat);
  156. writel(stat, &regs->isr); /* clear isr */
  157. return -EIO;
  158. }
  159. *retlen = len;
  160. return 0;
  161. }
  162. static void altera_qspi_sync(struct mtd_info *mtd)
  163. {
  164. }
  165. static void altera_qspi_get_locked_range(struct mtd_info *mtd, loff_t *ofs,
  166. uint64_t *len)
  167. {
  168. struct udevice *dev = mtd->dev;
  169. struct altera_qspi_platdata *pdata = dev_get_platdata(dev);
  170. struct altera_qspi_regs *regs = pdata->regs;
  171. int shift0 = ffs(QUADSPI_SR_BP2_0) - 1;
  172. int shift3 = ffs(QUADSPI_SR_BP3) - 1 - 3;
  173. u32 stat = readl(&regs->rd_status);
  174. unsigned pow = ((stat & QUADSPI_SR_BP2_0) >> shift0) |
  175. ((stat & QUADSPI_SR_BP3) >> shift3);
  176. *ofs = 0;
  177. *len = 0;
  178. if (pow) {
  179. *len = mtd->erasesize << (pow - 1);
  180. if (*len > mtd->size)
  181. *len = mtd->size;
  182. if (!(stat & QUADSPI_SR_TB))
  183. *ofs = mtd->size - *len;
  184. }
  185. }
  186. static int altera_qspi_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
  187. {
  188. struct udevice *dev = mtd->dev;
  189. struct altera_qspi_platdata *pdata = dev_get_platdata(dev);
  190. struct altera_qspi_regs *regs = pdata->regs;
  191. u32 sector_start, sector_end;
  192. u32 num_sectors;
  193. u32 mem_op;
  194. u32 sr_bp;
  195. u32 sr_tb;
  196. num_sectors = mtd->size / mtd->erasesize;
  197. sector_start = ofs / mtd->erasesize;
  198. sector_end = (ofs + len) / mtd->erasesize;
  199. if (sector_start >= num_sectors / 2) {
  200. sr_bp = fls(num_sectors - 1 - sector_start) + 1;
  201. sr_tb = 0;
  202. } else if (sector_end < num_sectors / 2) {
  203. sr_bp = fls(sector_end) + 1;
  204. sr_tb = 1;
  205. } else {
  206. sr_bp = 15;
  207. sr_tb = 0;
  208. }
  209. mem_op = (sr_tb << 12) | (sr_bp << 8);
  210. mem_op |= QUADSPI_MEM_OP_SECTOR_PROTECT;
  211. debug("lock %08x\n", mem_op);
  212. writel(mem_op, &regs->mem_op);
  213. return 0;
  214. }
  215. static int altera_qspi_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
  216. {
  217. struct udevice *dev = mtd->dev;
  218. struct altera_qspi_platdata *pdata = dev_get_platdata(dev);
  219. struct altera_qspi_regs *regs = pdata->regs;
  220. u32 mem_op;
  221. mem_op = QUADSPI_MEM_OP_SECTOR_PROTECT;
  222. debug("unlock %08x\n", mem_op);
  223. writel(mem_op, &regs->mem_op);
  224. return 0;
  225. }
  226. static int altera_qspi_probe(struct udevice *dev)
  227. {
  228. struct altera_qspi_platdata *pdata = dev_get_platdata(dev);
  229. struct altera_qspi_regs *regs = pdata->regs;
  230. unsigned long base = (unsigned long)pdata->base;
  231. struct mtd_info *mtd;
  232. flash_info_t *flash = &flash_info[0];
  233. u32 rdid;
  234. int i;
  235. rdid = readl(&regs->rd_rdid);
  236. debug("rdid %x\n", rdid);
  237. mtd = dev_get_uclass_priv(dev);
  238. mtd->dev = dev;
  239. mtd->name = "nor0";
  240. mtd->type = MTD_NORFLASH;
  241. mtd->flags = MTD_CAP_NORFLASH;
  242. mtd->size = 1 << ((rdid & 0xff) - 6);
  243. mtd->writesize = 1;
  244. mtd->writebufsize = mtd->writesize;
  245. mtd->_erase = altera_qspi_erase;
  246. mtd->_read = altera_qspi_read;
  247. mtd->_write = altera_qspi_write;
  248. mtd->_sync = altera_qspi_sync;
  249. mtd->_lock = altera_qspi_lock;
  250. mtd->_unlock = altera_qspi_unlock;
  251. mtd->numeraseregions = 0;
  252. mtd->erasesize = 0x10000;
  253. if (add_mtd_device(mtd))
  254. return -ENOMEM;
  255. flash->mtd = mtd;
  256. flash->size = mtd->size;
  257. flash->sector_count = mtd->size / mtd->erasesize;
  258. flash->flash_id = rdid;
  259. flash->start[0] = base;
  260. for (i = 1; i < flash->sector_count; i++)
  261. flash->start[i] = flash->start[i - 1] + mtd->erasesize;
  262. gd->bd->bi_flashstart = base;
  263. return 0;
  264. }
  265. static int altera_qspi_ofdata_to_platdata(struct udevice *dev)
  266. {
  267. struct altera_qspi_platdata *pdata = dev_get_platdata(dev);
  268. void *blob = (void *)gd->fdt_blob;
  269. int node = dev->of_offset;
  270. const char *list, *end;
  271. const fdt32_t *cell;
  272. void *base;
  273. unsigned long addr, size;
  274. int parent, addrc, sizec;
  275. int len, idx;
  276. /*
  277. * decode regs. there are multiple reg tuples, and they need to
  278. * match with reg-names.
  279. */
  280. parent = fdt_parent_offset(blob, node);
  281. of_bus_default_count_cells(blob, parent, &addrc, &sizec);
  282. list = fdt_getprop(blob, node, "reg-names", &len);
  283. if (!list)
  284. return -ENOENT;
  285. end = list + len;
  286. cell = fdt_getprop(blob, node, "reg", &len);
  287. if (!cell)
  288. return -ENOENT;
  289. idx = 0;
  290. while (list < end) {
  291. addr = fdt_translate_address((void *)blob,
  292. node, cell + idx);
  293. size = fdt_addr_to_cpu(cell[idx + addrc]);
  294. base = map_physmem(addr, size, MAP_NOCACHE);
  295. len = strlen(list);
  296. if (strcmp(list, "avl_csr") == 0) {
  297. pdata->regs = base;
  298. } else if (strcmp(list, "avl_mem") == 0) {
  299. pdata->base = base;
  300. pdata->size = size;
  301. }
  302. idx += addrc + sizec;
  303. list += (len + 1);
  304. }
  305. return 0;
  306. }
  307. static const struct udevice_id altera_qspi_ids[] = {
  308. { .compatible = "altr,quadspi-1.0" },
  309. {}
  310. };
  311. U_BOOT_DRIVER(altera_qspi) = {
  312. .name = "altera_qspi",
  313. .id = UCLASS_MTD,
  314. .of_match = altera_qspi_ids,
  315. .ofdata_to_platdata = altera_qspi_ofdata_to_platdata,
  316. .platdata_auto_alloc_size = sizeof(struct altera_qspi_platdata),
  317. .probe = altera_qspi_probe,
  318. };